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MT29C8G96MAYBADJV-5 WT

MT29C8G96MAYBADJV-5 WT

  • 厂商:

    MICRON(镁光)

  • 封装:

    VFBGA168

  • 描述:

    IC FLASH/LPDRAM 12GBIT 168VFBGA

  • 数据手册
  • 价格&库存
MT29C8G96MAYBADJV-5 WT 数据手册
Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Features NAND Flash and Mobile LPDDR 168-Ball Package-on-Package (PoP) MCP Combination Memory (TI OMAPŒ) MT29C4G48MAYBAAKQ-5 WT, MT29C4G48MAZBAAKQ-5 WT, MT29C4G96MAYBACJG-5 WT, MT29C4G96MAZBACJG-5 WT, MT29C8G96MAYBADJV-5 WT, MT29C8G96MAZBADJV-5 WT MT29C4G48MAZBAAKQ-5 IT, MT29C4G96MAZBACJG-5 IT MT29C8G96MAZBADJV-5 IT Features Figure 1: PoP Block Diagram MicronŠ NAND Flash and LPDDR components RoHS-compliant, “green” package Separate NAND Flash and LPDDR interfaces Space-saving multichip package/package-on-package combination • Low-voltage operation (1.70–1.95V) • Wireless temperature range: –25°C to +85°C • Industrial temperature range: –40°C to +85°C NAND Flash Power • • • • NAND Flash Device NAND Flash Interface NAND Flash-Specific Features Organization • Page size – x8: 2112 bytes (2048 + 64 bytes) – x16: 1056 words (1024 + 32 words) • Block size: 64 pages (128K + 4K bytes) LPDRAM Power LPDRAM Device LPDRAM Interface Mobile LPDDR-Specific Features • • • • • • • • No external voltage reference required No minimum clock rate requirement 1.8V LVCMOS-compatible inputs Programmable burst lengths Partial-array self refresh (PASR) Deep power-down (DPD) mode Selectable output drive strength STATUS REGISTER READ (SRR) supported1 Notes: 1. Contact factory for remapped SRR output. 2. For physical part markings, see on page . PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 1 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Features Part Numbering Information Micron NAND Flash and LPDRAM devices are available in different configurations and densities. The MCP/PoP part numbering guide is available at www.micron.com/numbering. Figure 2: Part Number Chart MT 29C XX XXX X X X X XX -X XX XX Micron Technology Production Status Product Family Operating Temperature Range NAND Flash Density LPDRAM Access Time LPDRAM Density Package Codes Operating Voltage Range Chip Count NAND Flash Configuration LPDRAM Configuration Device Marking Due to the size of the package, the Micron-standard part number is not printed on the top of the device. Instead, an abbreviated device mark consisting of a 5-digit alphanumeric code is used. The abbreviated device marks are cross-referenced to the Micron part numbers at the FBGA Part Marking Decoder site: www.micron.com/decoder. To view the location of the abbreviated mark on the device, refer to customer service note CSN-11, “Product Mark/ Label,” at www.micron.com/csn. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 2 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Features Contents MCP General Description ............................................................................................................................... Ball Assignments and Descriptions ................................................................................................................. Electrical Specifications .................................................................................................................................. Device Diagrams ............................................................................................................................................ Package Dimensions ....................................................................................................................................... 4Gb, 8Gb: x8, x16 NAND Flash Memory ........................................................................................................... Features ..................................................................................................................................................... General Description ....................................................................................................................................... Architecture ................................................................................................................................................... Device and Array Organization ........................................................................................................................ Asynchronous Interface Bus Operation ........................................................................................................... Asynchronous Enable/Standby ................................................................................................................... Asynchronous Commands .......................................................................................................................... Asynchronous Addresses ............................................................................................................................ Asynchronous Data Input ........................................................................................................................... Asynchronous Data Output ......................................................................................................................... Write Protect# ............................................................................................................................................ Ready/Busy# .............................................................................................................................................. Device Initialization ....................................................................................................................................... Command Definitions .................................................................................................................................... Reset Operations ............................................................................................................................................ RESET (FFh) ............................................................................................................................................... Identification Operations ................................................................................................................................ READ ID (90h) ............................................................................................................................................ READ ID Parameter Tables .............................................................................................................................. READ PARAMETER PAGE (ECh) ...................................................................................................................... Bare Die Parameter Page Data Structure Tables ................................................................................................ READ UNIQUE ID (EDh) ................................................................................................................................ Feature Operations ......................................................................................................................................... SET FEATURES (EFh) .................................................................................................................................. GET FEATURES (EEh) ................................................................................................................................. Status Operations ........................................................................................................................................... READ STATUS (70h) ................................................................................................................................... READ STATUS ENHANCED (78h) ................................................................................................................ Column Address Operations ........................................................................................................................... RANDOM DATA READ (05h-E0h) ................................................................................................................ RANDOM DATA READ TWO-PLANE (06h-E0h) ............................................................................................ RANDOM DATA INPUT (85h) ...................................................................................................................... PROGRAM FOR INTERNAL DATA INPUT (85h) ........................................................................................... Read Operations ............................................................................................................................................. READ MODE (00h) ..................................................................................................................................... READ PAGE (00h-30h) ................................................................................................................................ READ PAGE CACHE SEQUENTIAL (31h) ...................................................................................................... READ PAGE CACHE RANDOM (00h-31h) .................................................................................................... READ PAGE CACHE LAST (3Fh) .................................................................................................................. READ PAGE TWO-PLANE 00h-00h-30h ....................................................................................................... Program Operations ....................................................................................................................................... PROGRAM PAGE (80h-10h) ......................................................................................................................... PROGRAM PAGE CACHE (80h-15h) ............................................................................................................. PROGRAM PAGE TWO-PLANE (80h-11h) .................................................................................................... PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 3 11 12 16 17 19 22 22 23 24 25 29 29 29 31 32 33 34 34 39 40 43 43 44 44 45 48 49 52 53 54 55 58 59 59 61 61 62 63 64 66 68 68 69 70 72 73 75 76 76 79 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Features Erase Operations ............................................................................................................................................ 81 ERASE BLOCK (60h-D0h) ............................................................................................................................ 81 ERASE BLOCK TWO-PLANE (60h-D1h) ....................................................................................................... 82 Internal Data Move Operations ....................................................................................................................... 83 READ FOR INTERNAL DATA MOVE (00h-35h) ............................................................................................. 84 PROGRAM FOR INTERNAL DATA MOVE (85h–10h) ..................................................................................... 85 PROGRAM FOR INTERNAL DATA MOVE TWO-PLANE (85h-11h) ................................................................. 86 Block Lock Feature ......................................................................................................................................... 87 WP# and Block Lock ................................................................................................................................... 87 UNLOCK (23h-24h) .................................................................................................................................... 87 LOCK (2Ah) ................................................................................................................................................ 90 LOCK TIGHT (2Ch) ..................................................................................................................................... 91 BLOCK LOCK READ STATUS (7Ah) .............................................................................................................. 92 One-Time Programmable (OTP) Operations .................................................................................................... 94 Legacy OTP Commands .............................................................................................................................. 94 OTP DATA PROGRAM (80h-10h) ................................................................................................................. 95 RANDOM DATA INPUT (85h) ...................................................................................................................... 96 OTP DATA PROTECT (80h-10) ..................................................................................................................... 97 OTP DATA READ (00h-30h) ......................................................................................................................... 99 Two-Plane Operations ................................................................................................................................... 101 Two-Plane Addressing ............................................................................................................................... 101 Interleaved Die (Multi-LUN) Operations ......................................................................................................... 110 Error Management ........................................................................................................................................ 111 Internal ECC and Spare Area Mapping for ECC ............................................................................................... 113 Electrical Specifications ................................................................................................................................. 115 Electrical Specifications – DC Characteristics and Operating Conditions .......................................................... 117 Electrical Specifications – AC Characteristics and Operating Conditions .......................................................... 119 Electrical Specifications – Program/Erase Characteristics ................................................................................ 122 Asynchronous Interface Timing Diagrams ...................................................................................................... 123 2Gb: x16, x32 Mobile LPDDR SDRAM ............................................................................................................. 135 Features .................................................................................................................................................... 135 General Description .................................................................................................................................. 137 Functional Block Diagrams ............................................................................................................................ 138 Electrical Specifications ................................................................................................................................. 140 Electrical Specifications – IDD Parameters ....................................................................................................... 143 Electrical Specifications – AC Operating Conditions ........................................................................................ 149 Output Drive Characteristics .......................................................................................................................... 154 Functional Description .................................................................................................................................. 157 Commands ................................................................................................................................................... 158 DESELECT ................................................................................................................................................ 159 NO OPERATION ........................................................................................................................................ 159 LOAD MODE REGISTER ............................................................................................................................ 159 ACTIVE ..................................................................................................................................................... 159 READ ........................................................................................................................................................ 160 WRITE ...................................................................................................................................................... 161 PRECHARGE ............................................................................................................................................. 162 BURST TERMINATE .................................................................................................................................. 163 AUTO REFRESH ........................................................................................................................................ 163 SELF REFRESH .......................................................................................................................................... 164 DEEP POWER-DOWN ................................................................................................................................ 164 Truth Tables .................................................................................................................................................. 165 State Diagram ............................................................................................................................................... 170 PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 4 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Features Initialization ................................................................................................................................................. 171 Standard Mode Register ................................................................................................................................. 174 Burst Length ............................................................................................................................................. 175 Burst Type ................................................................................................................................................. 175 CAS Latency .............................................................................................................................................. 176 Operating Mode ........................................................................................................................................ 177 Extended Mode Register ................................................................................................................................ 178 Temperature-Compensated Self Refresh ..................................................................................................... 178 Partial-Array Self Refresh ........................................................................................................................... 179 Output Drive Strength ............................................................................................................................... 179 Status Read Register ...................................................................................................................................... 180 Bank/Row Activation ..................................................................................................................................... 182 READ Operation ............................................................................................................................................ 183 WRITE Operation .......................................................................................................................................... 194 PRECHARGE Operation ................................................................................................................................. 206 Auto Precharge .............................................................................................................................................. 206 Concurrent Auto Precharge ........................................................................................................................ 207 AUTO REFRESH Operation ............................................................................................................................ 213 SELF REFRESH Operation .............................................................................................................................. 214 Power-Down ................................................................................................................................................. 215 Deep Power-Down .................................................................................................................................... 217 Clock Change Frequency ............................................................................................................................... 219 Revision History ............................................................................................................................................ 220 Rev. C – 12/12 ............................................................................................................................................ 220 Rev. B – 10/12 ............................................................................................................................................ 220 Rev. A – 05/11 ............................................................................................................................................ 220 PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 5 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Features List of Figures Figure 1: PoP Block Diagram ............................................................................................................................ 1 Figure 2: Part Number Chart ............................................................................................................................ 2 Figure 3: 168-Ball VFBGA (NAND x8, x16; LPDDR x32) Ball Assignments .......................................................... 12 Figure 4: 168-Ball (Single LPDDR) Functional Block Diagram .......................................................................... 17 Figure 5: 168-Ball (Dual LPDDR) Functional Block Diagram ............................................................................ 18 Figure 6: 168-Ball VFBGA (Package Code: JG) .................................................................................................. 19 Figure 7: 168-Ball VFBGA (Package Code: JV) .................................................................................................. 20 Figure 8: 168-Ball WFBGA (Package Code: KQ) ................................................................................................ 21 Figure 9: NAND Flash Die (LUN) Functional Block Diagram ............................................................................ 24 Figure 10: Array Organization – MT29F4G08 (x8) ............................................................................................ 25 Figure 11: Array Organization – MT29F4G16 (x16) .......................................................................................... 26 Figure 12: Array Organization – MT29F8G08 and MT29F16G08 (x8) ................................................................. 27 Figure 13: Array Organization – MT29F8G16 (x16) .......................................................................................... 28 Figure 14: Asynchronous Command Latch Cycle ............................................................................................ 30 Figure 15: Asynchronous Address Latch Cycle ................................................................................................ 31 Figure 16: Asynchronous Data Input Cycles .................................................................................................... 32 Figure 17: Asynchronous Data Output Cycles ................................................................................................. 33 Figure 18: Asynchronous Data Output Cycles (EDO Mode) ............................................................................. 34 Figure 19: READ/BUSY# Open Drain .............................................................................................................. 35 Figure 20: tFall and tRise (3.3V V CC) ................................................................................................................ 36 Figure 21: tFall and tRise (1.8V V CC) ................................................................................................................ 36 Figure 22: IOL vs. Rp (VCC = 3.3V V CC) .............................................................................................................. 37 Figure 23: IOL vs. Rp (1.8V V CC) ....................................................................................................................... 37 Figure 24: TC vs. Rp ....................................................................................................................................... 38 Figure 25: R/B# Power-On Behavior ............................................................................................................... 39 Figure 26: RESET (FFh) Operation .................................................................................................................. 43 Figure 27: READ ID (90h) with 00h Address Operation .................................................................................... 44 Figure 28: READ ID (90h) with 20h Address Operation .................................................................................... 44 Figure 29: READ PARAMETER (ECh) Operation .............................................................................................. 48 Figure 30: READ UNIQUE ID (EDh) Operation ............................................................................................... 52 Figure 31: SET FEATURES (EFh) Operation .................................................................................................... 54 Figure 32: GET FEATURES (EEh) Operation .................................................................................................... 55 Figure 33: READ STATUS (70h) Operation ...................................................................................................... 59 Figure 34: READ STATUS ENHANCED (78h) Operation ................................................................................... 60 Figure 35: RANDOM DATA READ (05h-E0h) Operation ................................................................................... 61 Figure 36: RANDOM DATA READ TWO-PLANE (06h-E0h) Operation .............................................................. 62 Figure 37: RANDOM DATA INPUT (85h) Operation ........................................................................................ 63 Figure 38: PROGRAM FOR INTERNAL DATA INPUT (85h) Operation .............................................................. 65 Figure 39: READ PAGE (00h-30h) Operation ................................................................................................... 69 Figure 40: READ PAGE (00h-30h) Operation with Internal ECC Enabled .......................................................... 69 Figure 41: READ PAGE CACHE SEQUENTIAL (31h) Operation ......................................................................... 70 Figure 42: READ PAGE CACHE RANDOM (00h-31h) Operation ....................................................................... 71 Figure 43: READ PAGE CACHE LAST (3Fh) Operation ..................................................................................... 72 Figure 44: READ PAGE TWO-PLANE (00h-00h-30h) Operation ........................................................................ 74 Figure 45: PROGRAM PAGE (80h-10h) Operation ............................................................................................ 76 Figure 46: PROGRAM PAGE CACHE (80h–15h) Operation (Start) ..................................................................... 78 Figure 47: PROGRAM PAGE CACHE (80h–15h) Operation (End) ...................................................................... 78 Figure 48: PROGRAM PAGE TWO-PLANE (80h–11h) Operation ....................................................................... 80 Figure 49: ERASE BLOCK (60h-D0h) Operation .............................................................................................. 81 Figure 50: ERASE BLOCK TWO-PLANE (60h–D1h) Operation .......................................................................... 82 PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 6 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Features Figure 51: READ FOR INTERNAL DATA MOVE (00h-35h) Operation ................................................................ 84 Figure 52: READ FOR INTERNAL DATA MOVE (00h–35h) with RANDOM DATA READ (05h–E0h) ..................... 84 Figure 53: INTERNAL DATA MOVE (85h-10h) with Internal ECC Enabled ........................................................ 85 Figure 54: INTERNAL DATA MOVE (85h-10h) with RANDOM DATA INPUT with Internal ECC Enabled ............ 85 Figure 55: PROGRAM FOR INTERNAL DATA MOVE (85h–10h) Operation ........................................................ 85 Figure 56: PROGRAM FOR INTERNAL DATA MOVE (85h-10h) with RANDOM DATA INPUT (85h) .................... 86 Figure 57: PROGRAM FOR INTERNAL DATA MOVE TWO-PLANE (85h-11h) Operation .................................... 86 Figure 58: Flash Array Protected: Invert Area Bit = 0 ........................................................................................ 88 Figure 59: Flash Array Protected: Invert Area Bit = 1 ........................................................................................ 88 Figure 60: UNLOCK Operation ....................................................................................................................... 89 Figure 61: LOCK Operation ............................................................................................................................ 90 Figure 62: LOCK TIGHT Operation ................................................................................................................. 91 Figure 63: PROGRAM/ERASE Issued to Locked Block ...................................................................................... 92 Figure 64: BLOCK LOCK READ STATUS .......................................................................................................... 92 Figure 65: BLOCK LOCK Flowchart ................................................................................................................ 93 Figure 66: OTP DATA PROGRAM (After Entering OTP Operation Mode) ........................................................... 96 Figure 67: OTP DATA PROGRAM Operation with RANDOM DATA INPUT (After Entering OTP Operation Mode) ... 97 Figure 68: OTP DATA PROTECT Operation (After Entering OTP Protect Mode) ................................................. 98 Figure 69: OTP DATA READ ........................................................................................................................... 99 Figure 70: OTP DATA READ with RANDOM DATA READ Operation ................................................................ 100 Figure 71: TWO-PLANE PAGE READ ............................................................................................................. 102 Figure 72: TWO-PLANE PAGE READ with RANDOM DATA READ ................................................................... 103 Figure 73: TWO-PLANE PROGRAM PAGE ...................................................................................................... 103 Figure 74: TWO-PLANE PROGRAM PAGE with RANDOM DATA INPUT .......................................................... 104 Figure 75: TWO-PLANE PROGRAM PAGE CACHE MODE ............................................................................... 105 Figure 76: TWO-PLANE INTERNAL DATA MOVE ........................................................................................... 106 Figure 77: TWO-PLANE INTERNAL DATA MOVE with TWO-PLANE RANDOM DATA READ ............................ 107 Figure 78: TWO-PLANE INTERNAL DATA MOVE with RANDOM DATA INPUT ............................................... 108 Figure 79: TWO-PLANE BLOCK ERASE ......................................................................................................... 109 Figure 80: TWO-PLANE/MULTIPLE-DIE READ STATUS Cycle ........................................................................ 109 Figure 81: Spare Area Mapping (x8) ............................................................................................................... 113 Figure 82: Spare Area Mapping (x16) ............................................................................................................. 114 Figure 83: RESET Operation .......................................................................................................................... 123 Figure 84: READ STATUS Cycle ..................................................................................................................... 123 Figure 85: READ STATUS ENHANCED Cycle .................................................................................................. 124 Figure 86: READ PARAMETER PAGE ............................................................................................................. 124 Figure 87: READ PAGE .................................................................................................................................. 125 Figure 88: READ PAGE Operation with CE# “Don’t Care” ............................................................................... 126 Figure 89: RANDOM DATA READ .................................................................................................................. 127 Figure 90: READ PAGE CACHE SEQUENTIAL ................................................................................................ 128 Figure 91: READ PAGE CACHE RANDOM ...................................................................................................... 129 Figure 92: READ ID Operation ...................................................................................................................... 130 Figure 93: PROGRAM PAGE Operation .......................................................................................................... 130 Figure 94: PROGRAM PAGE Operation with CE# “Don’t Care” ........................................................................ 131 Figure 95: PROGRAM PAGE Operation with RANDOM DATA INPUT .............................................................. 131 Figure 96: PROGRAM PAGE CACHE .............................................................................................................. 132 Figure 97: PROGRAM PAGE CACHE Ending on 15h ........................................................................................ 132 Figure 98: INTERNAL DATA MOVE ............................................................................................................... 133 Figure 99: INTERNAL DATA MOVE (85h-10h) with Internal ECC Enabled ....................................................... 133 Figure 100: INTERNAL DATA MOVE (85h-10h) with Random Data Input with Internal ECC Enabled ............... 134 Figure 101: ERASE BLOCK Operation ............................................................................................................ 134 Figure 102: Functional Block Diagram (x16) .................................................................................................. 138 PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 7 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Features Figure 103: Figure 104: Figure 105: Figure 106: Figure 107: Figure 108: Figure 109: Figure 110: Figure 111: Figure 112: Figure 113: Figure 114: Figure 115: Figure 116: Figure 117: Figure 118: Figure 119: Figure 120: Figure 121: Figure 122: Figure 123: Figure 124: Figure 125: Figure 126: Figure 127: Figure 128: Figure 129: Figure 130: Figure 131: Figure 132: Figure 133: Figure 134: Figure 135: Figure 136: Figure 137: Figure 138: Figure 139: Figure 140: Figure 141: Figure 142: Figure 143: Figure 144: Figure 145: Figure 146: Figure 147: Figure 148: Figure 149: Functional Block Diagram (x32) .................................................................................................. 139 Typical Self Refresh Current vs. Temperature ................................................................................ 148 ACTIVE Command ..................................................................................................................... 160 READ Command ........................................................................................................................ 161 WRITE Command ....................................................................................................................... 162 PRECHARGE Command ............................................................................................................. 163 DEEP POWER-DOWN Command ................................................................................................ 164 Simplified State Diagram ............................................................................................................ 170 Initialize and Load Mode Registers .............................................................................................. 172 Alternate Initialization with CKE LOW ......................................................................................... 173 Standard Mode Register Definition .............................................................................................. 174 CAS Latency ............................................................................................................................... 177 Extended Mode Register ............................................................................................................. 178 Status Read Register Timing ........................................................................................................ 180 Status Register Definition ............................................................................................................ 181 READ Burst ................................................................................................................................ 184 Consecutive READ Bursts ............................................................................................................ 185 Nonconsecutive READ Bursts ...................................................................................................... 186 Random Read Accesses ............................................................................................................... 187 Terminating a READ Burst ........................................................................................................... 188 READ-to-WRITE ......................................................................................................................... 189 READ-to-PRECHARGE ................................................................................................................ 190 Data Output Timing – tDQSQ, tQH, and Data Valid Window (x16) ................................................. 191 Data Output Timing – tDQSQ, tQH, and Data Valid Window (x32) ................................................. 192 Data Output Timing – tAC and tDQSCK ........................................................................................ 193 Data Input Timing ...................................................................................................................... 195 Write – DM Operation ................................................................................................................. 196 WRITE Burst ............................................................................................................................... 197 Consecutive WRITE-to-WRITE .................................................................................................... 198 Nonconsecutive WRITE-to-WRITE .............................................................................................. 198 Random WRITE Cycles ............................................................................................................... 199 WRITE-to-READ – Uninterrupting ............................................................................................... 200 WRITE-to-READ – Interrupting ................................................................................................... 201 WRITE-to-READ – Odd Number of Data, Interrupting .................................................................. 202 WRITE-to-PRECHARGE – Uninterrupting .................................................................................... 203 WRITE-to-PRECHARGE – Interrupting ........................................................................................ 204 WRITE-to-PRECHARGE – Odd Number of Data, Interrupting ....................................................... 205 Bank Read – With Auto Precharge ................................................................................................ 208 Bank Read – Without Auto Precharge ........................................................................................... 210 Bank Write – With Auto Precharge ............................................................................................... 211 Bank Write – Without Auto Precharge .......................................................................................... 212 Auto Refresh Mode ..................................................................................................................... 213 Self Refresh Mode ....................................................................................................................... 215 Power-Down Entry (in Active or Precharge Mode) ........................................................................ 216 Power-Down Mode (Active or Precharge) ..................................................................................... 217 Deep Power-Down Mode ............................................................................................................ 218 Clock Stop Mode ........................................................................................................................ 219 PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 8 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Features List of Tables Table 1: x8, x16 NAND Ball Descriptions ......................................................................................................... 13 Table 2: x32 LPDDR Ball Descriptions ............................................................................................................ 14 Table 3: Non-Device-Specific Descriptions ..................................................................................................... 15 Table 4: Absolute Maximum Ratings .............................................................................................................. 16 Table 5: Recommended Operating Conditions ................................................................................................ 16 Table 6: Array Addressing – MT29F4G08 (x8) .................................................................................................. 25 Table 7: Array Addressing – MT29F4G16 (x16) ................................................................................................. 26 Table 8: Array Addressing – MT29F8G08 and MT29F16G08 (x8) ....................................................................... 27 Table 9: Array Addressing – MT29F8G16 ( x16) ................................................................................................ 28 Table 10: Asynchronous Interface Mode Selection .......................................................................................... 29 Table 11: Command Set ................................................................................................................................. 40 Table 12: Two-Plane Command Set ................................................................................................................ 42 Table 13: READ ID Parameters for Address 00h ............................................................................................... 45 Table 14: READ ID Parameters for Address 20h ............................................................................................... 47 Table 15: Parameter Page Data Structure ........................................................................................................ 49 Table 16: Feature Address Definitions ............................................................................................................. 53 Table 17: Feature Address 90h – Array Operation Mode ................................................................................... 54 Table 18: Feature Addresses 01h: Timing Mode ............................................................................................... 56 Table 19: Feature Addresses 80h: Programmable I/O Drive Strength ................................................................ 57 Table 20: Feature Addresses 81h: Programmable R/B# Pull-Down Strength ...................................................... 57 Table 21: Status Register Definition ................................................................................................................ 58 Table 22: Block Lock Address Cycle Assignments ............................................................................................ 89 Table 23: Block Lock Status Register Bit Definitions ........................................................................................ 92 Table 24: Error Management Details ............................................................................................................. 111 Table 25: Absolute Maximum Ratings ............................................................................................................ 115 Table 26: Recommended Operating Conditions ............................................................................................. 115 Table 27: Valid Blocks ................................................................................................................................... 115 Table 28: Capacitance ................................................................................................................................... 116 Table 29: Test Conditions .............................................................................................................................. 116 Table 30: DC Characteristics and Operating Conditions (3.3V) ....................................................................... 117 Table 31: DC Characteristics and Operating Conditions (1.8V) ....................................................................... 118 Table 32: AC Characteristics: Command, Data, and Address Input (3.3V) ........................................................ 119 Table 33: AC Characteristics: Command, Data, and Address Input (1.8V) ........................................................ 119 Table 34: AC Characteristics: Normal Operation (3.3V) .................................................................................. 120 Table 35: AC Characteristics: Normal Operation (1.8V) .................................................................................. 120 Table 36: Program/Erase Characteristics ....................................................................................................... 122 Table 37: Configuration Addressing – 2Gb ..................................................................................................... 136 Table 38: Absolute Maximum Ratings ............................................................................................................ 140 Table 39: AC/DC Electrical Characteristics and Operating Conditions ............................................................ 140 Table 40: Capacitance (x16, x32) ................................................................................................................... 142 Table 41: IDD Specifications and Conditions, –25°C to +85°C (x16) .................................................................. 143 Table 42: IDD Specifications and Conditions, –25°C to +85°C (x32) .................................................................. 144 Table 43: IDD Specifications and Conditions, –40°C to +105°C (x16) ................................................................. 145 Table 44: IDD Specifications and Conditions, –40°C to +105°C (x32) ................................................................. 146 Table 45: IDD6 Specifications and Conditions ................................................................................................. 147 Table 46: Electrical Characteristics and Recommended AC Operating Conditions ........................................... 149 Table 47: Target Output Drive Characteristics (Full Strength) .......................................................................... 154 Table 48: Target Output Drive Characteristics (Three-Quarter Strength) ......................................................... 155 Table 49: Target Output Drive Characteristics (One-Half Strength) ................................................................. 156 Table 50: Truth Table – Commands ............................................................................................................... 158 PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 9 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Features Table 51: Table 52: Table 53: Table 54: Table 55: DM Operation Truth Table ............................................................................................................. 159 Truth Table – Current State Bank n – Command to Bank n ............................................................... 165 Truth Table – Current State Bank n – Command to Bank m .............................................................. 167 Truth Table – CKE .......................................................................................................................... 169 Burst Definition Table .................................................................................................................... 175 PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 10 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP MCP General Description MCP General Description Micron package-on-package (PoP) MCP products combine NAND Flash and Mobile LPDRAM devices in a single MCP. These products target mobile applications with lowpower, high-performance, and minimal package-footprint design requirements. The NAND Flash and Mobile LPDRAM devices are also members of the Micron discrete memory products portfolio. The NAND Flash and Mobile LPDRAM devices are packaged with separate interfaces (no shared address, control, data, or power balls). This bus architecture supports an optimized interface to processors with separate NAND Flash and Mobile LPDRAM buses. The NAND Flash and Mobile LPDRAM devices have separate core power connections and share a common ground (that is, V SS is tied together on the two devices). The bus architecture of this device also supports separate NAND Flash and Mobile LPDRAM functionality without concern for device interaction. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 11 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Ball Assignments and Descriptions Ball Assignments and Descriptions Figure 3: 168-Ball VFBGA (NAND x8, x16; LPDDR x32) Ball Assignments 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18 17 19 20 21 22 23 A DNU DNU DQ17 VDDQ DQ19 DM2 VDDQ DQ21 DQ23 VDDQ CK VDD DQ9 DQ11 VDDQ DQ13 DM1 VDDQ DQ15 DM3 DQ25 DNU DNU A B DNU DNU DQ16 VSSQ DQ18 DQS2 VSSQ DQ20 DQ22 VSSQ CK# VSS DQ8 DQ10 VSSQ DQ12 DQS1 VSSQ DQ14 DQS3 DQ24 DNU DNU B C DM0 DQS0 VSSQ VDDQ C D DQ7 DQ6 DQ26 DQ27 D E VDDQ VSSQ DQ28 DQ29 E F DQ5 DQ4 VSSQ VDDQ F G DQ3 DQ2 DQ30 DQ31 G H VDDQ VSSQ J DQ1 DQ0 K VDD VSS L VCC M VSS VDD CKE0 CKE1 VSS H J WE# K VSS CAS# RAS# L I/O1 I/O0 CS0# CS1# M N I/O3 I/O2 A0 A1 N P VCC VSS A2 A3 P R I/O5 I/O4 A4 A5 R T I/O7 I/O6 A6 A7 T U VCC VSS A8 A9 U V WE# RE# A10 A11 V W ALE NC A12 A13 W Y CE1# CE0# A14 VDD Y AA VCC VSS VSS VDD AA AB DNU DNU I/O8 I/O10 VSS I/O12 I/O14 VSS AC DNU DNU I/O9 I/O11 VCC I/O13 I/O15 VCC NC 1 2 3 4 6 8 9 5 7 NC R/B# VSS VSS NC NC NC NC NC VSS BA0 DNU DNU AB NC NC CLE VCC TQ NC NC NC NC NC NC BA1 DNU DNU AC 10 11 12 13 14 15 16 17 18 19 20 21 22 23 LOCK WP# Top View – Ball Down PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 12 NAND LPDDR Supply Ground Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Ball Assignments and Descriptions Table 1: x8, x16 NAND Ball Descriptions Note: Symbol Type ALE Input Address latch enable: When ALE is HIGH, addresses can be transferred to the on-chip address register. Description CE0#, CE1# Input Chip enable: Gates transfers between the host system and the NAND device. CE1# is used when a second CE# is required and is RFU1 in all other configurations. CLE Input Command latch enable: When CLE is HIGH, commands can be transferred to the on-chip command register. LOCK Input When LOCK is HIGH during power-up, the BLOCK LOCK function is enabled. To disable BLOCK LOCK, connect LOCK to VSS during power-up, or leave it unconnected (internal pulldown). RE# Input Read enable: Gates information from the NAND device to the host system. WE# Input Write enable: Gates information from the host system to the NAND device. WP# Input Write protect: Driving WP# LOW blocks ERASE and PROGRAM operations. I/O[15:0] Input/ output Data inputs/outputs: The bidirectional I/Os transfer address, data, and instruction information. Data is output only during READ operations; at other times the I/Os are inputs. I/O[15:8] are RFU for x8 NAND devices. R/B# Output Ready/busy: Open-drain, active-LOW output that indicates when an internal operation is in progress. VCC Supply VCC: NAND power supply. 1. Balls marked RFU may or may not be connected internally. These balls should not be used. Contact factory for details. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 13 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Ball Assignments and Descriptions Table 2: x32 LPDDR Ball Descriptions Note: Symbol Type Description A[14:0] Input Address inputs: Specifies the row or column address. Also used to load the mode registers. The maximum LPDDR address is determined by density and configuration. Consult the LPDDR product data sheet for the maximum address for a given density and configuration. Unused address balls become RFU.1 BA0, BA1 Input Bank address inputs: Specifies one of the 4 banks. CAS# Input Column select: Specifies which command to execute. CK, CK# Input CK is the system clock. CK and CK# are differential clock inputs. All address and control signals are sampled and referenced on the crossing of the rising edge of CK with the falling edge of CK#. CKE0, CKE1 Input Clock enable. CKE0 is used for a single LPDDR product. CKE1 is used for dual LPDDR products and is considered RFU for single LPDDR MCPs. CS0#, CS1# Input Chip select: CS0# is used for a single LPDDR product. CS1# is used for dual LPDDR products and is considered RFU for single LPDDR MCPs. DM[3:0] Input Data mask: Determines which bytes are written during WRITE operations. RAS# Input Row select: Specifies the command to execute. WE# Input Write enable: Specifies the command to execute. DQ[31:0] Input/ output Data bus: Data inputs/outputs. DQS[3:0] Input/ output Data strobe: Coordinates READ/WRITE transfers of data; one DQS per DQ byte. TQ Output Temperature sensor output: TQ HIGH when LPDDR TJ exceeds 85°C. VDD Supply VDD: LPDDR power supply. VDDQ Supply VDDQ: LPDDR I/O power supply. VSSQ Supply VSSQ: LPDDR I/O ground. 1. Balls marked RFU may or may not be connected internally. These balls should not be used. Contact factory for details. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 14 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Ball Assignments and Descriptions Table 3: Non-Device-Specific Descriptions Note: Symbol Type VSS Supply Description Symbol Type DNU – Do not use: Must be grounded or left floating. NC – No connect: Not internally connected. RFU1 – Reserved for future use. VSS: Shared ground. Description 1. Balls marked RFU may or may not be connected internally. These balls should not be used. Contact factory for details. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 15 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Electrical Specifications Electrical Specifications Table 4: Absolute Maximum Ratings Parameters/Conditions Symbol Min Max Unit VCC, VDD, VDDQ supply voltage relative to VSS VCC, VDD, VDDQ –1.0 2.4 V VIN –0.5 2.4 or (supply voltage1 + 0.3V), whichever is less V –55 +150 °C Voltage on any pin relative to VSS Storage temperature range Note: 1. Supply voltage references VCC, VDD, or VDDQ. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Table 5: Recommended Operating Conditions Parameters Symbol Min Typ Max Unit Supply voltage VCC, VDD 1.70 1.80 1.95 V VDDQ 1.70 1.80 1.95 V – –25 – +85 °C I/O supply voltage Operating temperature range PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 16 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Device Diagrams Device Diagrams Figure 4: 168-Ball (Single LPDDR) Functional Block Diagram CE0# VCC CLE ALE RE# NAND Flash I/O WE# WP# R/B# LOCK VSS CS0# VDD CK VDDQ CK# CKE0 DM LPDDR RAS# DQ CAS# WE# DQS TQ Address, VSS BA0, BA1 PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 VSSQ 17 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Device Diagrams Figure 5: 168-Ball (Dual LPDDR) Functional Block Diagram CE0# VCC CLE ALE NAND Flash RE# I/O WE# WP# R/B# VSS CS0, CS1# VDD CK VDDQ CK# DM LPDDR CKE0, CKE1 (Die 0 and 1) RAS# DQ CAS# WE# DQS TQ Address, VSS BA0, BA1 PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 VSSQ 18 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Package Dimensions Package Dimensions Figure 6: 168-Ball VFBGA (Package Code: JG) Seating plane 0.08 A 0.58 ±0.05 A 168X Ø0.34 Solder ball material: SAC105. Dimensions apply to solder balls postreflow on Ø0.28 SMD ball pads. Ball A1 ID Ball A1 ID 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC 11 CTR 12 ±0.1 0.9 MAX 0.5 TYP 0.5 TYP 11 CTR 0.23 MIN 12 ±0.1 Note: 1. All dimensions are in millimeters. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 19 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Package Dimensions Figure 7: 168-Ball VFBGA (Package Code: JV) Seating plane 0.08 A 0.68 ±0.05 A 168X Ø0.34 Solder ball material: SAC105. Dimensions apply S to solder balls post- R reflow on Ø0.28 SMD ball pads. Ball A1 ID Ball A1 ID 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC 11 CTR 12 ±0.1 1.0 MAX 0.5 TYP 0.5 TYP 11 CTR 0.23 MIN 12 ±0.1 Note: 1. All dimensions are in millimeters. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 20 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Package Dimensions Figure 8: 168-Ball WFBGA (Package Code: KQ) Seating plane 0.08 A 0.43 ±0.05 A 168X Ø0.34 Solder ball material: SAC105. Dimensions apply S to solder balls post- R reflow on Ø0.28 SMD ball pads. Ball A1 ID Ball A1 ID 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC 11 CTR 12 ±0.1 0.75 MAX 0.5 TYP 0.5 TYP 11 CTR 0.23 MIN 12 ±0.1 Note: 1. All dimensions are in millimeters. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 21 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP 4Gb, 8Gb: x8, x16 NAND Flash Memory 4Gb, 8Gb: x8, x16 NAND Flash Memory Features • Open NAND Flash Interface (ONFI) 1.0-compliant1 • Single-level cell (SLC) technology • Organization – Page size x8: 2112 bytes (2048 + 64 bytes) – Page size x16: 1056 words (1024 + 32 words) – Block size: 64 pages (128K + 4K bytes) – Plane size: 2 planes x 2048 blocks per plane – Device size: 4Gb: 4096 blocks; 8Gb: 8192 blocks • Asynchronous I/O performance – tRC/tWC: 20ns (3.3V), 25ns (1.8V) • Array performance – Read page: 25μs2 – Program page: 200μs (TYP: 1.8V, 3.3V)2 – Erase block: 700μs (TYP) • Command set: ONFI NAND Flash Protocol • Advanced command set – Program page cache mode3 – Read page cache mode3 – One-time programmable (OTP) mode – Two-plane commands3 – Interleaved die (LUN) operations – Read unique ID – Block lock (1.8V only) – Internal data move • Operation status byte provides software method for detecting – Operation completion – Pass/fail condition – Write-protect status • Ready/Busy# (R/B#) signal provides a hardware method of detecting operation completion • WP# signal: Write protect entire device • Blocks 0–15 (block addresses 00h–0Fh) are valid when shipped from factory with ECC; for minimum required ECC, see Error Management • Block 0 requires 1-bit ECC if PROGRAM/ERASE cycles are less than 1000 • RESET (FFh) required as first command after power-on • Alternate method of device initialization (Nand_Init) after power-up (contact factory) • Internal data move operations supported within the plane from which data is read • Quality and reliability – Data retention: 10 years • Operating voltage range – VCC: 2.7–3.6V – VCC: 1.7–1.95V • Operating temperature – Commercial: 0°C to +70°C – Industrial (IT): –40ºC to +85ºC Notes: 1. The ONFI 1.0 specification is available at www.onfi.org. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 22 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP General Description 2. See Electrical Specifications – Program/Erase Characteristics (page 122) for tR_ECC and tPROG_ECC specifications. 3. These commands supported only with ECC disabled. General Description Micron NAND Flash devices include an asynchronous data interface for high-performance I/O operations. These devices use a highly multiplexed 8-bit bus (I/Ox) to transfer commands, address, and data. There are five control signals used to implement the asynchronous data interface: CE#, CLE, ALE, WE#, and RE#. Additional signals control hardware write protection and monitor device status (R/B#). This hardware interface creates a low pin-count device with a standard pinout that remains the same from one density to another, enabling future upgrades to higher densities with no board redesign. A target is the unit of memory accessed by a chip enable signal. A target contains one or more NAND Flash die. A NAND Flash die is the minimum unit that can independently execute commands and report status. A NAND Flash die, in the ONFI specification, is referred to as a logical unit (LUN). There is at least one NAND Flash die per chip enable signal. For further details, see Device and Array Organization. This device has an internal 4-bit ECC that can be enabled using the GET/SET features. See Internal ECC and Spare Area Mapping for ECC for more information. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 23 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Architecture Architecture These devices use NAND Flash electrical and command interfaces. Data, commands, and addresses are multiplexed onto the same pins and received by I/O control circuits. The commands received at the I/O control circuits are latched by a command register and are transferred to control logic circuits for generating internal signals to control device operations. The addresses are latched by an address register and sent to a row decoder to select a row address, or to a column decoder to select a column address. Data is transferred to or from the NAND Flash memory array, byte by byte (x8) or word by word (x16), through a data register and a cache register. The NAND Flash memory array is programmed and read using page-based operations and is erased using block-based operations. During normal page operations, the data and cache registers act as a single register. During cache operations, the data and cache registers operate independently to increase data throughput. The status register reports the status of die operations. Figure 9: NAND Flash Die (LUN) Functional Block Diagram VCC I/Ox I/O control VSS Address register Status register Command register CE# Column decode CLE WE# Control logic Row decode ALE RE# WP# LOCK1 NAND Flash array (2 planes) Data register R/B# Cache register ECC Note: 1. The LOCK pin is used on the 1.8V device. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 24 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Device and Array Organization Device and Array Organization Figure 10: Array Organization – MT29F4G08 (x8) 2112 bytes 2112 bytes DQ7 Cache Register 2048 64 2048 64 Data Register 2048 64 2048 64 2048 blocks per plane 1 block DQ0 1 page = (2K + 64 bytes) 1 block = (2K + 64) bytes x 64 pages = (128K + 4K) bytes 1 plane = (128K + 4K) bytes x 2048 blocks = 2112Mb 1 block 4096 blocks per device 1 device = 2112Mb x 2 planes = 4224Mb Plane of even-numbered blocks (0, 2, 4, 6, ..., 4092, 4094) Plane of odd-numbered blocks (1, 3, 5, 7, ..., 4093, 4095) Table 6: Array Addressing – MT29F4G08 (x8) Cycle I/07 I/06 I/05 I/04 I/03 I/02 I/01 I/00 First CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0 Second LOW LOW LOW LOW CA11 CA10 CA9 CA8 Third BA7 BA6 PA5 PA4 PA3 PA2 PA1 PA0 Fourth BA15 BA14 BA13 BA12 BA11 BA10 BA9 BA8 Fifth LOW LOW LOW LOW LOW LOW BA17 BA16 Notes: 1. Block address concatenated with page address = actual page address. CAx = column address; PAx = page address; BAx = block address. 2. If CA11 is 1, then CA[10:6] must be 0. 3. BA6 controls plane selection. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 25 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Device and Array Organization Figure 11: Array Organization – MT29F4G16 (x16) 1056 words 1056 words DQ15 Cache Register 1024 32 1024 32 Data Register 1024 32 1024 32 2048 blocks per plane 1 block DQ0 1 page = (1K + 32 words) 1 block = (1K + 32) words x 64 pages = (64K + 2K) words 1 plane = (64K + 2K) words x 2048 blocks = 2112Mb 1 device = 2112Mb x 2 planes = 4224Mb 1 block 4096 blocks per device Plane of even-numbered blocks (0, 2, 4, 6, ..., 4092, 4094) Plane of odd-numbered blocks (1, 3, 5, 7, ..., 4093, 4095) Table 7: Array Addressing – MT29F4G16 (x16) Cycle I/O[15:8] I/07 I/06 I/05 I/04 I/03 I/02 I/01 I/00 First LOW CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0 Second LOW LOW LOW LOW LOW LOW CA10 CA9 CA8 Third LOW BA7 BA6 PA5 PA4 PA3 PA2 PA1 PA0 Fourth LOW BA15 BA14 BA13 BA12 BA11 BA10 BA9 BA8 Fifth LOW LOW LOW LOW LOW LOW LOW BA17 BA16 Notes: 1. Block address concatenated with page address = actual page address. CAx = column address; PAx = page address; BAx = block address. 2. If CA10 = 1, then CA[9:5] must be 0. 3. BA6 controls plane selection. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 26 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Device and Array Organization Figure 12: Array Organization – MT29F8G08 and MT29F16G08 (x8) Die 0 2112 bytes Die 1 2112 bytes 2112 bytes 2112 bytes I/O7 Cache Register 2048 64 2048 64 2048 64 2048 64 Data Register 2048 64 2048 64 2048 64 2048 64 I/O0 1 page = (2K + 64 bytes) 2048 blocks per plane 1 block 1 block 1 block 1 block 1 block = (2K + 64) bytes x 64 pages = (128K + 4K) bytes 1 plane = (128K + 4K) bytes x 2048 blocks = 2112Mb 4096 blocks per die 1 die Plane 0: evennumbered blocks (0, 2, 4, 6, ..., 4092, 4094)1 Note: Plane 1: oddnumbered blocks (1, 3, 5, 7, ..., 4093, 4095) Plane 0: evennumbered blocks (4096, 4098, ..., 8188, 8190) Plane 1: oddnumbered blocks (4097, 4099, ..., 8189, 8191) = 2112Mb x 2 planes = 4224Mb 1 device = 4224Mb x 2 die = 8448Mb 1. Die 0, Plane 0: BA18 = 0; BA6 = 0. Die 0, Plane 1: BA18 = 0; BA6 = 1. Die 1, Plane 0: BA18 = 1; BA6 = 0. Die 1, Plane 1: BA18 = 1; BA6 = 1. Table 8: Array Addressing – MT29F8G08 and MT29F16G08 (x8) Cycle I/07 I/06 I/05 I/04 I/03 I/02 I/01 I/00 First CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0 Second LOW LOW LOW LOW CA11 CA10 CA9 CA8 Third BA7 BA6 PA5 PA4 PA3 PA2 PA1 PA0 Fourth BA15 BA14 BA13 BA12 BA11 BA10 BA9 BA8 Fifth LOW LOW LOW LOW LOW BA183 BA17 BA16 Notes: 1. CAx = column address; PAx = page address; BAx = block address. 2. If CA11 is 1, then CA[10:6] must be 0. 3. Die address boundary: 0 = 0–4Gb; 1 = 4Gb–8Gb. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 27 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Device and Array Organization Figure 13: Array Organization – MT29F8G16 (x16) Die 0 1056 words Die 1 1056 words 1056 words 1056 words I/O7 Cache Register 1024 32 1024 32 1024 32 1024 32 Data Register 1024 32 1024 32 1024 32 1024 32 I/O0 1 page = (1K + 32 words) 2048 blocks per plane 1 block 1 block 1 block 1 block 1 block = (1K + 32) words x 64 pages = (64K + 2K) words 1 plane = (128K + 4K) bytes x 2048 blocks = 2112Mb 4096 blocks per die 1 die Plane 0: evennumbered blocks (0, 2, 4, 6, ..., 4092, 4094)1 Note: Plane 1: oddnumbered blocks (1, 3, 5, 7, ..., 4093, 4095) Plane 0: evennumbered blocks (4096, 4098, ..., 8188, 8190) Plane 1: oddnumbered blocks (4097, 4099, ..., 8189, 8191) = 2112Mb x 2 planes = 4224Mb 1 device = 4224Mb x 2 die = 8448Mb 1. Die 0, Plane 0: BA18 = 0; BA6 = 0. Die 0, Plane 1: BA18 = 0; BA6 = 1. Die 1, Plane 0: BA18 = 1; BA6 = 0. Die 1, Plane 1: BA18 = 1; BA6 = 1. Table 9: Array Addressing – MT29F8G16 ( x16) Cycle I/O[15:8] I/07 I/06 I/05 I/04 I/03 I/02 I/01 I/O0 First LOW CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0 Second LOW LOW LOW LOW LOW LOW CA10 CA9 CA8 Third LOW BA7 BA6 PA5 PA4 PA3 PA2 PA1 PA0 Fourth LOW BA15 BA14 BA13 BA12 BA11 BA10 BA9 PA8 Fifth LOW LOW LOW LOW LOW LOW BA183 BA17 BA16 Notes: 1. Block address concatenated with page address = actual page address. CAx = column address; PAx = page address; BAx = block address. 2. If CA10 = 1, then CA[9:5] must be 0. 3. Die address boundary: 0 = 0–4Gb; 1 = 4Gb–8Gb. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 28 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Asynchronous Interface Bus Operation Asynchronous Interface Bus Operation The bus on the device is multiplexed. Data I/O, addresses, and commands all share the same pins. I/O[15:8] are used only for data in the x16 configuration. Addresses and commands are always supplied on I/O[7:0]. The command sequence typically consists of a COMMAND LATCH cycle, address input cycles, and one or more data cycles, either READ or WRITE. Table 10: Asynchronous Interface Mode Selection Mode1 CE# CLE ALE WE# RE# I/Ox WP# Standby2 H X X X X X 0V/VCC Command input L H L H X H Address input L L H H X H Data input L L L H X H Data output L L L H X X Write protect X X X X X L Notes: X 1. Mode selection settings for this table: H = Logic level HIGH; L = Logic level LOW; X = VIH or VIL. 2. WP# should be biased to CMOS LOW or HIGH for standby. Asynchronous Enable/Standby When the device is not performing an operation, the CE# pin is typically driven HIGH and the device enters standby mode. The memory will enter standby if CE# goes HIGH while data is being transferred and the device is not busy. This helps reduce power consumption. The CE# “Don’t Care” operation enables the NAND Flash to reside on the same asynchronous memory bus as other Flash or SRAM devices. Other devices on the memory bus can then be accessed while the NAND Flash is busy with internal operations. This capability is important for designs that require multiple NAND Flash devices on the same bus. A HIGH CLE signal indicates that a command cycle is taking place. A HIGH ALE signal signifies that an ADDRESS INPUT cycle is occurring. Asynchronous Commands An asynchronous command is written from I/O[7:0] to the command register on the rising edge of WE# when CE# is LOW, ALE is LOW, CLE is HIGH, and RE# is HIGH. Commands are typically ignored by die (LUNs) that are busy (RDY = 0); however, some commands, including READ STATUS (70h) and READ STATUS ENHANCED (78h), are accepted by die (LUNs) even when they are busy. For devices with a x16 interface, I/O[15:8] must be written with zeros when a command is issued. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 29 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Asynchronous Interface Bus Operation Figure 14: Asynchronous Command Latch Cycle CLE tCLS tCS tCLH tCH CE# tWP WE# tALS tALH tDS tDH ALE I/Ox COMMAND Don’t Care PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 30 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Asynchronous Interface Bus Operation Asynchronous Addresses An asynchronous address is written from I/O[7:0] to the address register on the rising edge of WE# when CE# is LOW, ALE is HIGH, CLE is LOW, and RE# is HIGH. Bits that are not part of the address space must be LOW (see Device and Array Organization). The number of cycles required for each command varies. Refer to the command descriptions to determine addressing requirements. Addresses are typically ignored by die (LUNs) that are busy (RDY = 0); however, some addresses are accepted by die (LUNs) even when they are busy; for example, like address cycles that follow the READ STATUS ENHANCED (78h) command. Figure 15: Asynchronous Address Latch Cycle CLE tCLS tCS CE# tWC tWP tWH WE# tALS tALH ALE tDS tDH I/Ox Col add 1 Col add 2 Row add 1 Row add 2 Don’t Care PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 31 Row add 3 Undefined Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Asynchronous Interface Bus Operation Asynchronous Data Input Data is written from I/O[7:0] to the cache register of the selected die (LUN) on the rising edge of WE# when CE# is LOW, ALE is LOW, CLE is LOW, and RE# is HIGH. Data input is ignored by die (LUNs) that are not selected or are busy (RDY = 0). Data is written to the data register on the rising edge of WE# when CE#, CLE, and ALE are LOW, and the device is not busy. Data is input on I/O[7:0] on x8 devices and on I/O[15:0] on x16 devices. Figure 16: Asynchronous Data Input Cycles CLE tCLH CE# tALS tCH ALE tWC tWP tWP tWP WE# tWH tDS I/Ox tDH DIN M tDS tDH DIN M+1 tDS tDH DIN N Don’t Care PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 32 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Asynchronous Interface Bus Operation Asynchronous Data Output Data can be output from a die (LUN) if it is in a READY state. Data output is supported following a READ operation from the NAND Flash array. Data is output from the cache register of the selected die (LUN) to I/O[7:0] on the falling edge of RE# when CE# is LOW, ALE is LOW, CLE is LOW, and WE# is HIGH. If the host controller is using a tRC of 30ns or greater, the host can latch the data on the rising edge of RE# (see the figure below for proper timing). If the host controller is using a tRC of less than 30ns, the host can latch the data on the next falling edge of RE#. Using the READ STATUS ENHANCED (78h) command prevents data contention following an interleaved die (multi-LUN) operation. After issuing the READ STATUS ENHANCED (78h) command, to enable data output, issue the READ MODE (00h) command. Data output requests are typically ignored by a die (LUN) that is busy (RDY = 0); however, it is possible to output data from the status register even when a die (LUN) is busy by first issuing the READ STATUS or READ STATUS ENHANCED (78h) command. Figure 17: Asynchronous Data Output Cycles tCEA CE# tREA tREA tRP tCHZ tREA tREH tCOH RE# tRHZ tRHZ tRHOH DOUT I/Ox tRR DOUT DOUT tRC RDY Don’t Care PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 33 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Asynchronous Interface Bus Operation Figure 18: Asynchronous Data Output Cycles (EDO Mode) CE# tRC tRP tCHZ tREH tCOH RE# tREA tCEA I/Ox tREA tRHZ tRLOH tRHOH DOUT DOUT DOUT tRR RDY Don’t Care Write Protect# The write protect# (WP#) signal enables or disables PROGRAM and ERASE operations to a target. When WP# is LOW, PROGRAM and ERASE operations are disabled. When WP# is HIGH, PROGRAM and ERASE operations are enabled. It is recommended that the host drive WP# LOW during power-on until V CC is stable to prevent inadvertent PROGRAM and ERASE operations (see Device Initialization for additional details). WP# must be transitioned only when the target is not busy and prior to beginning a command sequence. After a command sequence is complete and the target is ready, WP# can be transitioned. After WP# is transitioned, the host must wait tWW before issuing a new command. The WP# signal is always an active input, even when CE# is HIGH. This signal should not be multiplexed with other signals. Ready/Busy# The ready/busy# (R/B#) signal provides a hardware method of indicating whether a target is ready or busy. A target is busy when one or more of its die (LUNs) are busy (RDY = 0). A target is ready when all of its die (LUNs) are ready (RDY = 1). Because each die (LUN) contains a status register, it is possible to determine the independent status of each die (LUN) by polling its status register instead of using the R/B# signal (see Status Operations for details regarding die (LUN) status). This signal requires a pull-up resistor, Rp, for proper operation. R/B# is HIGH when the target is ready, and transitions LOW when the target is busy. The signal's open-drain PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 34 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Asynchronous Interface Bus Operation driver enables multiple R/B# outputs to be OR-tied. Typically, R/B# is connected to an interrupt pin on the system controller. The combination of Rp and capacitive loading of the R/B# circuit determines the rise time of the R/B# signal. The actual value used for Rp depends on the system timing requirements. Large values of Rp cause R/B# to be delayed significantly. Between the 10% and 90% points on the R/B# waveform, the rise time is approximately two time constants (TC). TC = R × C Where R = Rp (resistance of pull-up resistor), and C = total capacitive load. The fall time of the R/B# signal is determined mainly by the output impedance of the R/B# signal and the total load capacitance. Approximate Rp values using a circuit load of 100pF are provided in Figure 24 (page 38). The minimum value for Rp is determined by the output drive capability of the R/B# signal, the output voltage swing, and V CC. VCC (MAX) - VOL (MAX) IOL + ȈIL Where ȈIL is the sum of the input currents of all devices tied to the R/B# pin. Rp = Figure 19: READ/BUSY# Open Drain Rp VCC R/B# Open drain output IOL VSS Device PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 35 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Asynchronous Interface Bus Operation Figure 20: tFall and tRise (3.3V VCC) 3.50 3.00 2.50 tFall tRise 2.00 V 1.50 1.00 0.50 0.00 –1 0 2 4 0 2 4 TC Notes: 6 VCC 3.3V 1. tFall and tRise calculated at 10% and 90% points. 2. tRise dependent on external capacitance and resistive loading and output transistor impedance. 3. tRise primarily dependent on external pull-up resistor and external capacitive loading. 4. tFall = 10ns at 3.3V. 5. See TC values in Figure 24 (page 38) for approximate Rp value and TC. Figure 21: tFall and tRise (1.8V VCC) 3.50 3.00 2.50 tFall 2.00 tRise V 1.50 1.00 0.50 0.00 -1 0 2 4 0 TC Notes: 1. 2. 3. 4. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 2 4 6 VCC1.8V tFall and tRise are calculated at 10% and 90% points. is primarily dependent on external pull-up resistor and external capacitive loading. tFall ≈ 7ns at 1.8V. See TC values in Figure 24 (page 38) for TC and approximate Rp value. tRise 36 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Asynchronous Interface Bus Operation Figure 22: IOL vs. Rp (VCC = 3.3V VCC) 3.50 3.00 2.50 2.00 , P$ 1.50 1.00 0.50 0.00 0 2000 400 0 6000 8000 10,000 12,000 Rp (ȍ) IOL at VCC (MAX) Figure 23: IOL vs. Rp (1.8V VCC) 3.50 3.00 2.50 2.00 I (mA) 1.50 1.00 0.50 0.00 0 2000 4000 6000 8000 10,000 12,000 Rp (ȍ) IOL at VCC (MAX) PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 37 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Asynchronous Interface Bus Operation Figure 24: TC vs. Rp 1200 1000 800 T(ns) 600 400 200 0 0200040006000800010,00012,000 Rp (ȍ) PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 38 IOL at VCC (MAX) RC = TC C = 100pF Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Device Initialization Device Initialization Micron NAND Flash devices are designed to prevent data corruption during power transitions. V CC is internally monitored. (The WP# signal supports additional hardware protection during power transitions.) When ramping V CC, use the following procedure to initialize the device: 1. Ramp V CC. 2. The host must wait for R/B# to be valid and HIGH before issuing RESET (FFh) to any target. The R/B# signal becomes valid when 50μs has elapsed since the beginning the V CC ramp, and 10μs has elapsed since V CC reaches V CC (MIN). 3. If not monitoring R/B#, the host must wait at least 100μs after V CC reaches V CC (MIN). If monitoring R/B#, the host must wait until R/B# is HIGH. 4. The asynchronous interface is active by default for each target. Each LUN draws less than an average of 10mA (IST) measured over intervals of 1ms until the RESET (FFh) command is issued. 5. The RESET (FFh) command must be the first command issued to all targets (CE#s) after the NAND Flash device is powered on. Each target will be busy for 1ms after a RESET command is issued. The RESET busy time can be monitored by polling R/B# or issuing the READ STATUS (70h) command to poll the status register. 6. The device is now initialized and ready for normal operation. Figure 25: R/B# Power-On Behavior 50μs (MIN) VCC VCC = VCC (MIN) 10μs (MAX) R/B# 100μs (MAX) VCC ramp starts Reset (FFh) is issued Invalid PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 39 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Command Definitions Command Definitions Table 11: Command Set Command Cycle #1 Number of Valid Address Cycles Data Input Cycles FFh 0 – – Yes Yes READ ID 90h 1 – – No No READ PARAMETER PAGE ECh 1 – – No No READ UNIQUE ID EDh 1 – – No No GET FEATURES EEh 1 – – No No SET FEATURES EFh 1 4 – No No READ STATUS 70h 0 – – Yes READ STATUS ENHANCED 78h 3 – – Yes Yes Command Valid While Command Selected LUN is Busy1 Cycle #2 Valid While Other LUNs are Busy2 Notes Reset Operations RESET Identification Operation Feature Operations Status Operations Column Address Operations RANDOM DATA READ 05h 2 – E0h No Yes RANDOM DATA INPUT 85h 2 Optional – No Yes PROGRAM FOR INTERNAL DATA MOVE 85h 5 Optional – No Yes READ MODE 00h 0 – – No Yes READ PAGE 00h 5 – 30h No Yes READ PAGE CACHE SEQUENTIAL 31h 0 – – No Yes 4, 5 READ PAGE CACHE RANDOM 00h 5 – 31h No Yes 4, 5 READ PAGE CACHE LAST 3Fh 0 – – No Yes 4, 5 PROGRAM PAGE 80h 5 Yes 10h No Yes PROGRAM PAGE CACHE 80h 5 Yes 15h No Yes 60h 3 – D0h No Yes 5 – 35h No Yes 3 READ OPERATIONS Program Operations 4, 6 Erase Operations ERASE BLOCK Internal Data Move Operations READ FOR INTERNAL DATA MOVE 00h PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 40 3 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Command Definitions Table 11: Command Set (Continued) Command Cycle #1 Number of Valid Address Cycles Data Input Cycles 85h 5 Optional 10h No Yes 23h 3 – – No Yes BLOCK UNLOCK HIGH 24h 3 – – No Yes BLOCK LOCK 2Ah – – – No Yes BLOCK LOCK-TIGHT 2Ch – – – No Yes BLOCK LOCK READ STATUS 7Ah 3 – – No Yes Command PROGRAM FOR INTERNAL DATA MOVE Valid While Command Selected LUN is Busy1 Cycle #2 Valid While Other LUNs are Busy2 Notes Block Lock Operations BLOCK UNLOCK LOW One-Time Programmable (OTP) Operations OTP DATA LOCK BY PAGE (ONFI) 80h 5 No 10h No No 7 OTP DATA PROGRAM (ONFI) 80h 5 Yes 10h No No 7 OTP DATA READ (ONFI) 00h 5 No 30h No No 7 Notes: 1. Busy means RDY = 0. 2. These commands can be used for interleaved die (multi-LUN) operations (see Interleaved Die (Multi-LUN) Operations (page 110)). 3. Do not cross plane address boundaries when using READ for INTERNAL DATA MOVE and PROGRAM for INTERNAL DATA MOVE. 4. These commands supported only with ECC disabled. 5. Issuing a READ PAGE CACHE series (31h, 00h-31h, 3Fh) command when the array is busy (RDY = 1, ARDY = 0) is supported if the previous command was a READ PAGE (00h-30h) or READ PAGE CACHE series command; otherwise, it is prohibited. 6. Issuing a PROGRAM PAGE CACHE (80h-15h) command when the array is busy (RDY = 1, ARDY = 0) is supported if the previous command was a PROGRAM PAGE CACHE (80h-15h) command; otherwise, it is prohibited. 7. OTP commands can be entered only after issuing the SET FEATURES command with the feature address. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 41 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Command Definitions Table 12: Two-Plane Command Set Note 4 applies to all parameters and conditions Number of Valid ComAddress mand Cycles Cycle #1 Command Command Cycle #2 Number of Valid Address Cycles Command Cycle #3 Valid While Valid While Selected Other LUNs LUN is Busy are Busy Notes READ PAGE TWOPLANE 00h 5 00h 5 30h No Yes READ FOR TWOPLANE INTERNAL DATA MOVE 00h 5 00h 5 35h No Yes 1 RANDOM DATA READ TWO-PLANE 06h 5 E0h – – No Yes 2 PROGRAM PAGE TWO-PLANE 80h 5 11h-80h 5 10h No Yes PROGRAM PAGE CACHE MODE TWOPLANE 80h 5 11h-80h 5 15h No Yes PROGRAM FOR TWO-PLANE INTERNAL DATA MOVE 85h 5 11h-85h 5 10h No Yes 1 BLOCK ERASE TWOPLANE 60h 3 D1h-60h 3 D0h No Yes 3 Notes: 1. Do not cross plane boundaries when using READ FOR INTERNAL DATA MOVE TWOPLANE or PROGRAM FOR TWO-PLANE INTERNAL DATA MOVE. 2. The RANDOM DATA READ TWO-PLANE command is limited to use with the PAGE READ TWO-PLANE command. 3. D1h command can be omitted. 4. These commands supported only with ECC disabled. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 42 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Reset Operations Reset Operations RESET (FFh) The RESET command is used to put the memory device into a known condition and to abort the command sequence in progress. READ, PROGRAM, and ERASE commands can be aborted while the device is in the busy state. The contents of the memory location being programmed or the block being erased are no longer valid. The data may be partially erased or programmed, and is invalid. The command register is cleared and is ready for the next command. The data register and cache register contents are marked invalid. The status register contains the value E0h when WP# is HIGH; otherwise it is written with a 60h value. R/B# goes LOW for tRST after the RESET command is written to the command register. The RESET command must be issued to all CE#s as the first command after power-on. The device will be busy for a maximum of 1ms. Figure 26: RESET (FFh) Operation Cycle type I/O[7:0] Command FF tWB tRST R/B# PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 43 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Identification Operations Identification Operations READ ID (90h) The READ ID (90h) command is used to read identifier codes programmed into the target. This command is accepted by the target only when all die (LUNs) on the target are idle. Writing 90h to the command register puts the target in read ID mode. The target stays in this mode until another valid command is issued. When the 90h command is followed by an 00h address cycle, the target returns a 5-byte identifier code that includes the manufacturer ID, device configuration, and part-specific information. When the 90h command is followed by a 20h address cycle, the target returns the 4-byte ONFI identifier code. Figure 27: READ ID (90h) with 00h Address Operation Cycle type Command Address DOUT DOUT DOUT DOUT DOUT Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 tWHR I/O[7:0] Note: 90h 00h 1. See the READ ID Parameter tables for byte definitions. Figure 28: READ ID (90h) with 20h Address Operation Cycle type Command Address DOUT DOUT DOUT DOUT 4Fh 4Eh 46h 49h tWHR I/O[7:0] Note: 90h 20h 1. See READ ID Parameter tables for byte definitions. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 44 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP READ ID Parameter Tables READ ID Parameter Tables Table 13: READ ID Parameters for Address 00h b = binary; h = hexadecimal Options I/07 I/06 I/05 I/04 I/03 I/02 I/01 I/00 Value Micron 0 0 1 0 1 1 0 0 2Ch 4Gb, x8, 3.3V 1 1 0 1 1 1 0 0 DCh MT29F4G16ABADA 4Gb, x16, 3.3V 1 1 0 0 1 1 0 0 CCh MT29F4G08ABBDA 4Gb, x8, 1.8V 1 0 1 0 1 1 0 0 ACh MT29F4G16ABBDA 4Gb, x16, 1.8V 1 0 1 1 1 1 0 0 BCh MT29F8G08ADBDA 8Gb, x8, 1.8V 1 0 1 0 0 0 1 1 A3h MT29F8G16ADBDA 8Gb, x16, 1.8V 1 0 1 1 0 0 1 1 B3h MT29F8G08ADADA 8Gb, x8, 3.3V 1 1 0 1 0 0 1 1 D3h MT29F8G16ADADA 8Gb, x16, 3.3V 1 1 0 0 0 0 1 1 C3h MT29F16G08AJADA 16Gb, x8, 3.3V 1 1 0 1 0 0 1 1 D3h 1 0 0 00b 2 0 1 01b Byte 0 – Manufacturer ID Manufacturer Byte 1 – Device ID MT29F4G08ABADA Byte 2 Number of die per CE Cell type SLC 0 Number of simultaneously programmed pages 2 Interleaved operations between multiple die Not supported Cache programming Supported 1 Byte value MT29F4G08ABADA 1 0 0 1 0 0 0 0 90h MT29F4G16ABADA 1 0 0 1 0 0 0 0 90h MT29F4G08ABBDA 1 0 0 1 0 0 0 0 90h MT29F4G16ABBDA 1 0 0 1 0 0 0 0 90h MT29F8G08ADBDA 1 1 0 1 0 0 0 1 D1h MT29F8G16ADBDA 1 1 0 1 0 0 0 1 D1h MT29F8G08ADADA 1 1 0 1 0 0 0 1 D1h MT29F8G16ADADA 1 1 0 1 0 0 0 1 D1h MT29F16G08AJADA 1 1 0 1 0 0 0 1 D1h 0 1 01b 0 0 00b 1 01b 0 0b 1b Byte 3 Page size 2KB Spare area size (bytes) 64B Block size (without spare) 128KB Organization 1 0 1 1b 01b x8 0 0b x16 1 1b PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 45 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP READ ID Parameter Tables Table 13: READ ID Parameters for Address 00h (Continued) b = binary; h = hexadecimal Options Serial access (MIN) Byte value I/07 I/06 I/05 I/04 I/03 I/02 I/01 I/00 Value 1.8V 25ns 0 0 0xxx0b 3.3V 20ns 1 0 1xxx0b MT29F4G08ABADA 1 0 0 1 0 1 0 1 95h MT29F4G16ABADA 1 1 0 1 0 1 0 1 D5h MT29F4G08ABBDA 0 0 0 1 0 1 0 1 15h MT29F4G16ABBDA 0 1 0 1 0 1 0 1 55h MT29F8G08ADBDA 0 0 0 1 0 1 0 1 15h MT29F8G16ADBDA 0 1 0 1 0 1 0 1 55h MT29F8G08ADADA 1 0 0 1 0 1 0 1 95h MT29F8G16ADADA 1 1 0 1 0 1 0 1 D5h MT29F16G08AJADA 1 0 0 1 0 1 0 1 95h 1 0 10b Byte 4 Internal ECC level 4-bit ECC/512 (main) + 4 (spare) + 8 (parity) bytes Planes per CE# 2 4 0 1 1 0 01b 10b Plane size 2Gb Internal ECC ECC disabled 0 0b ECC enabled 1 1b Byte value 1 0 1 101b MT29F4G08ABADA 0 1 0 1 0 1 1 0 56h MT29F4G16ABADA 0 1 0 1 0 1 1 0 56h MT29F4G08ABBDA 0 1 0 1 0 1 1 0 56h MT29F4G16ABBDA 0 1 0 1 0 1 1 0 56h MT29F8G08ADBDA 0 1 0 1 1 0 1 0 5Ah MT29F8G16ADBDA 0 1 0 1 1 0 1 0 5Ah MT29F8G08ADADA 0 1 0 1 1 0 1 0 5Ah MT29F8G16ADADA 0 1 0 1 1 0 1 0 5Ah MT29F16G08AJADA 0 1 0 1 1 0 1 0 5Ah PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 46 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP READ ID Parameter Tables Table 14: READ ID Parameters for Address 20h h = hexadecimal Byte Options I/07 I/06 I/05 I/04 I/03 I/02 I/01 I/00 Value 0 “O” 0 1 0 0 1 1 1 1 4Fh 1 “N” 0 1 0 0 1 1 1 0 4Eh 2 “F” 0 1 0 0 0 1 1 0 46h 3 “I” 0 1 0 0 1 0 0 1 49h 4 Undefined X X X X X X X X XXh PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 47 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP READ PARAMETER PAGE (ECh) READ PARAMETER PAGE (ECh) The READ PARAMETER PAGE (ECh) command is used to read the ONFI parameter page programmed into the target. This command is accepted by the target only when all die (LUNs) on the target are idle. Writing ECh to the command register puts the target in read parameter page mode. The target stays in this mode until another valid command is issued. When the ECh command is followed by an 00h address cycle, the target goes busy for tR. If the READ STATUS (70h) command is used to monitor for command completion, the READ MODE (00h) command must be used to re-enable data output mode. Use of the READ STATUS ENHANCED (78h) command is prohibited while the target is busy and during data output. A minimum of three copies of the parameter page are stored in the device. Each parameter page is 256 bytes. If desired, the RANDOM DATA READ (05h-E0h) command can be used to change the location of data output. Figure 29: READ PARAMETER (ECh) Operation Cycle type I/O[7:0] Command Address ECh 00h tWB tR DOUT DOUT DOUT DOUT DOUT DOUT P00 P10 … P01 P11 … tRR R/B# PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 48 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Bare Die Parameter Page Data Structure Tables Bare Die Parameter Page Data Structure Tables Table 15: Parameter Page Data Structure Byte Description Value 0–3 Parameter page signature 4Fh, 4Eh, 46h, 49h 4–5 Revision number 6–7 Features supported 8–9 02h, 00h MT29F4G08ABBDA3W 18h, 00h MT29F4G16ABBDA3W 19h, 00h MT29F8G08ADBDA3W 1Ah, 00h MT29F8G16ADBDA3W 1Bh, 00h MT29F4G08ABADA3W 18h, 00h MT29F4G16ABADA3W 19h, 00h MT29F8G08ADADA3W 1Ah, 00h MT29F8G16ADADA3W 1Bh, 00h Optional commands supported 3Fh, 00h 10–31 Reserved 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h 32–43 Device manufacturer 4Dh, 49h, 43h, 52h, 4Fh, 4Eh, 20h, 20h, 20h, 20h, 20h, 20h 44–63 Device model 64 MT29F4G08ABBDA3W 4Dh, 54h, 32h, 39h, 46h, 34h, 47h, 30h, 38h, 41h, 42h, 42h, 44h, 41h, 33h, 57h, 20h, 20h, 20h, 20h MT29F4G16ABBDA3W 4Dh, 54h, 32h, 39h, 46h, 34h, 47h, 31h, 36h, 41h, 42h, 42h, 44h, 41h, 33h, 57h, 20h, 20h, 20h, 20h MT29F8G08ADBDA3W 4Dh, 54h, 32h, 39h, 46h, 38h, 47h, 30h, 38h, 41h, 44h, 42h, 44h, 41h, 33h, 57h, 20h, 20h, 20h, 20h MT29F8G16ADBDA3W 4Dh, 54h, 32h, 39h, 46h, 38h, 47h, 31h, 36h, 41h, 44h, 42h, 44h, 41h, 33h, 57h, 20h, 20h, 20h, 20h MT29F4G08ABADA3W 4Dh, 54h, 32h, 39h, 46h, 34h, 47h, 30h, 38h, 41h, 42h, 41h, 44h, 41h, 33h, 57h, 20h, 20h, 20h, 20h MT29F4G16ABADA3W 4Dh, 54h, 32h, 39h, 46h, 34h, 47h, 31h, 36h, 41h, 42h, 41h, 44h, 41h, 33h, 57h, 20h, 20h, 20h, 20h MT29F8G08ADADA3W 4Dh, 54h, 32h, 39h, 46h, 38h, 47h, 30h, 38h, 41h, 44h, 41h, 44h, 41h, 33h, 57h, 20h, 20h, 20h, 20h MT29F8G16ADADA3W 4Dh, 54h, 32h, 39h, 46h, 38h, 47h, 31h, 36h, 41h, 44h, 41h, 44h, 41h, 33h, 57h, 20h, 20h, 20h, 20h Manufacturer ID 2Ch 65–66 Date code 00h, 00h 67–79 Reserved 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h 80–83 Number of data bytes per page 00h, 08h, 00h, 00h 84–85 Number of spare bytes per page 40h, 00h 86–89 Number of data bytes per partial page 00h, 02h, 00h, 00h 90–91 Number of spare bytes per partial page 10h, 00h PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 49 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Bare Die Parameter Page Data Structure Tables Table 15: Parameter Page Data Structure (Continued) Byte Description Value 92–95 Number of pages per block 40h, 00h, 00h, 00h 96–99 Number of blocks per unit 00h, 10h, 00h, 00h 100 Number of logical units MT29F4G08ABBDA3W 01h MT29F4G16ABBDA3W 01h MT29F8G08ADBDA3W 02h MT29F8G16ADBDA3W 02h MT29F4G08ABADA3W 01h MT29F4G16ABADA3W 01h MT29F8G08ADADA3W 02h MT29F8G16ADADA3W 02h 101 Number of address cycles 23h 102 Number of bits per cell 01h 103–104 Bad blocks maximum per unit 50h, 00h 105–106 Block endurance 01h, 05h 107 Guaranteed valid blocks at beginning of target 01h 108–109 Block endurance for guaranteed valid blocks 00h, 00h 110 Number of programs per page 04h 111 Partial programming attributes 00h 112 Number of bits ECC bits 04h 113 Number of interleaved address bits 01h 114 Interleaved operation attributes 0Eh 115–127 Reserved 128 I/O pin capacitance PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h MT29F4G08ABBDA3W 0Ah MT29F4G16ABBDA3W 0Ah MT29F8G08ADBDA3W 14h MT29F8G16ADBDA3W 14h MT29F4G08ABADA3W 0Ah MT29F4G16ABADA3W 0Ah MT29F8G08ADADA3W 14h MT29F8G16ADADA3W 14h 50 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Bare Die Parameter Page Data Structure Tables Table 15: Parameter Page Data Structure (Continued) Byte Description 129–130 Timing mode support 131–132 Program cache timing mode support 133–134 tPROG 135–136 tBERS 137–138 tR 139–140 tCCs Value MT29F4G08ABBDA3W 1Fh, 00h MT29F4G16ABBDA3W 1Fh, 00h MT29F8G08ADBDA3W 1Fh, 00h MT29F8G16ADBDA3W 1Fh, 00h MT29F4G08ABADA3W 3Fh, 00h MT29F4G16ABADA3W 3Fh, 00h MT29F8G08ADADA3W 3Fh, 00h MT29F8G16ADADA3W 3Fh, 00h MT29F4G08ABBDA3W 1Fh, 00h MT29F4G16ABBDA3W 1Fh, 00h MT29F8G08ADBDA3W 1Fh, 00h MT29F8G16ADBDA3W 1Fh, 00h MT29F4G08ABADA3W 3Fh, 00h MT29F4G16ABADA3W 3Fh, 00h MT29F8G08ADADA3W 3Fh, 00h MT29F8G16ADADA3W 3Fh, 00h (MAX) page program time 58h, 02h (MAX) block erase time B8h, 0Bh (MAX) page read time 19h, 00h (MIN) 64h, 00h 141–163 Reserved 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h 164–165 Vendor-specific revision number 01h, 00h 166–253 Vendor-specific 01h, 00h, 00h, 02h, 04h, 80h, 01h, 81h, 04h, 01h, 02h, 01h,0Ah, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,00h, 00h, 00h, 00h 254–255 Integrity CRC Set at test 256–511 Value of bytes 0–255 512–767 Value of bytes 0–255 768+ Additional redundant parameter pages PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 51 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP READ UNIQUE ID (EDh) READ UNIQUE ID (EDh) The READ UNIQUE ID (EDh) command is used to read a unique identifier programmed into the target. This command is accepted by the target only when all die (LUNs) on the target are idle. Writing EDh to the command register puts the target in read unique ID mode. The target stays in this mode until another valid command is issued. When the EDh command is followed by an 00h address cycle, the target goes busy for If the READ STATUS (70h) command is used to monitor for command completion, the READ MODE (00h) command must be used to re-enable data output mode. tR. After tR completes, the host enables data output mode to read the unique ID. When the asynchronous interface is active, one data byte is output per RE# toggle. Sixteen copies of the unique ID data are stored in the device. Each copy is 32 bytes. The first 16 bytes of a 32-byte copy are unique data, and the second 16 bytes are the complement of the first 16 bytes. The host should XOR the first 16 bytes with the second 16 bytes. If the result is 16 bytes of FFh, then that copy of the unique ID data is correct. In the event that a non-FFh result is returned, the host can repeat the XOR operation on a subsequent copy of the unique ID data. If desired, the RANDOM DATA READ (05h-E0h) command can be used to change the data output location. The upper eight I/Os on a x16 device are not used and are a “Don’t Care” for x16 devices. Figure 30: READ UNIQUE ID (EDh) Operation Cycle type I/O[7:0] Command Address EDh 00h tWB tR DOUT DOUT DOUT DOUT DOUT DOUT U00 U10 … U01 U11 … tRR R/B# PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 52 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Feature Operations Feature Operations The SET FEATURES (EFh) and GET FEATURES (EEh) commands are used to modify the target's default power-on behavior. These commands use a one-byte feature address to determine which subfeature parameters will be read or modified. Each feature address (in the 00h to FFh range) is defined in below. The SET FEATURES (EFh) command writes subfeature parameters (P1–P4) to the specified feature address. The GET FEATURES command reads the subfeature parameters (P1–P4) at the specified feature address. When a feature is set, by default it remains active until the device is power cycled. It is volatile. Unless otherwise specified in the features table, once a device is set it remains set, even if a RESET (FFh) command is issued. GET/SET FEATURES commands can be used after required RESET to enable features before system BOOT ROM process. Internal ECC can be enabled/disabled using SET FEATURES (EFh). The SET FEATURES command (EFh), followed by address 90h, followed by four data bytes (only the first data byte is used) will enable/disable internal ECC. The sequence to enable internal ECC with SET FEATURES is EFh(cmd)-90h(addr)08h(data)-00h(data)-00h(data)-00h(data)-wait(tFEAT). The sequence to disable internal ECC with SET FEATURES is EFh(cmd)-90h(addr)00h(data)-00h(data)-00h(data)-00h(data)-wait(tFEAT). The GET FEATURES command is EEh. Table 16: Feature Address Definitions Feature Address Reserved 01h Timing mode 02h–7Fh Reserved 80h Programmable output drive strength 81h Programmable RB# pull-down strength 82h–FFh 90h PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 Definition 00h Reserved Array operation mode 53 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Feature Operations Table 17: Feature Address 90h – Array Operation Mode Subfeature Parameter Options 1/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Value Notes 1 P1 Operation mode option Normal Reserved (0) 0 00h OTP operation Reserved (0) 1 01h 1 1 03h OTP protection Reserved (0) Disable ECC Reserved (0) 0 0 0 0 00h 1 Enable ECC Reserved (0) 1 0 0 0 08h 1 P2 Reserved Reserved (0) 00h Reserved (0) 00h Reserved (0) 00h P3 Reserved P4 Reserved 1. These bits are reset to 00h on power cycle. Note: SET FEATURES (EFh) The SET FEATURES (EFh) command writes the subfeature parameters (P1–P4) to the specified feature address to enable or disable target-specific features. This command is accepted by the target only when all die (LUNs) on the target are idle. Writing EFh to the command register puts the target in the set features mode. The target stays in this mode until another command is issued. The EFh command is followed by a valid feature address. The host waits for tADL before the subfeature parameters are input. When the asynchronous interface is active, one subfeature parameter is latched per rising edge of WE#. After all four subfeature parameters are input, the target goes busy for tFEAT. The READ STATUS (70h) command can be used to monitor for command completion. Feature address 01h (timing mode) operation is unique. If SET FEATURES is used to modify the interface type, the target will be busy for tITC. Figure 31: SET FEATURES (EFh) Operation Cycle type Command Address DIN DIN DIN DIN P1 P2 P3 P4 tADL I/O[7:0] EFh FA tWB tFEAT R/B# PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 54 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Feature Operations GET FEATURES (EEh) The GET FEATURES (EEh) command reads the subfeature parameters (P1–P4) from the specified feature address. This command is accepted by the target only when all die (LUNs) on the target are idle. Writing EEh to the command register puts the target in get features mode. The target stays in this mode until another valid command is issued. When the EEh command is followed by a feature address, the target goes busy for tFEAT. If the READ STATUS (70h) command is used to monitor for command completion, the READ MODE (00h) command must be used to re-enable data output mode. After tFEAT completes, the host enables data output mode to read the subfeature parameters. Figure 32: GET FEATURES (EEh) Operation Cycle type I/Ox Command Address EEh FA tWB tFEAT DOUT DOUT DOUT DOUT P1 P2 P3 P4 tRR R/B# PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 55 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Feature Operations Table 18: Feature Addresses 01h: Timing Mode Subfeature Parameter Options I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Value Notes P1 Timing mode Mode 0 (default) Reserved (0) 0 0 0 00h 1, 2 Mode 1 Reserved (0) 0 0 1 01h 2 Mode 2 Reserved (0) 0 1 0 02h 2 Mode 3 Reserved (0) 0 1 1 03h 2 Mode 4 Reserved (0) 1 0 0 04h 2 Mode 5 Reserved (0) 1 0 1 05h 3 P2 Reserved (0) 00h Reserved (0) 00h Reserved (0) 00h P3 P4 Notes: 1. The timing mode feature address is used to change the default timing mode. The timing mode should be selected to indicate the maximum speed at which the device will receive commands, addresses, and data cycles. The five supported settings for the timing mode are shown. The default timing mode is mode 0. The device returns to mode 0 when the device is power cycled. Supported timing modes are reported in the parameter page. 2. Supported for both 1.8V and 3.3V. 3. Supported for 3.3V only. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 56 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Feature Operations Table 19: Feature Addresses 80h: Programmable I/O Drive Strength Subfeature Parameter Options I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Value Notes 1 P1 I/O drive strength Full (default) Reserved (0) 0 0 00h Three-quarters Reserved (0) 0 1 01h One-half Reserved (0) 1 0 02h One-quarter Reserved (0) 1 1 03h P2 Reserved (0) 00h Reserved (0) 00h Reserved (0) 00h P3 P4 Note: 1. The programmable drive strength feature address is used to change the default I/O drive strength. Drive strength should be selected based on expected loading of the memory bus. This table shows the four supported output drive strength settings. The default drive strength is full strength. The device returns to the default drive strength mode when the device is power cycled. AC timing parameters may need to be relaxed if I/O drive strength is not set to full. Table 20: Feature Addresses 81h: Programmable R/B# Pull-Down Strength Subfeature Parameter Options I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Value Notes 1 P1 R/B# pull-down strength Full (default) 0 0 00h Three-quarters 0 1 01h One-half 1 0 02h One-quarter 1 1 03h P2 Reserved (0) 00h Reserved (0) 00h Reserved (0) 00h P3 P4 Note: 1. This feature address is used to change the default R/B# pull-down strength. Its strength should be selected based on the expected loading of R/B#. Full strength is the default, power-on value. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 57 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Status Operations Status Operations Each die (LUN) provides its status independently of other die (LUNs) on the same target through its 8-bit status register. After the READ STATUS (70h) or READ STATUS ENHANCED (78h) command is issued, status register output is enabled. The contents of the status register are returned on I/ O[7:0] for each data output request. When the asynchronous interface is active and status register output is enabled, changes in the status register are seen on I/O[7:0] as long as CE# and RE# are LOW; it is not necessary to toggle RE# to see the status register update. While monitoring the status register to determine when a data transfer from the Flash array to the data register (tR) is complete, the host must issue the READ MODE (00h) command to disable the status register and enable data output (see Read Operations). The READ STATUS (70h) command returns the status of the most recently selected die (LUN). To prevent data contention during or following an interleaved die (multi-LUN) operation, the host must enable only one die (LUN) for status output by using the READ STATUS ENHANCED (78h) command (see Interleaved Die (Multi-LUN) Operations). With internal ECC enabled, a READ STATUS command is required after completion of the data transfer (tR_ECC) to determine whether an uncorrectable read error occurred. Table 21: Status Register Definition SR Bit Program Page Program Page Cache Mode Page Read Page Read Cache Mode 7 Write protect Write protect Write protect Write protect 6 RDY RDY1 cache RDY RDY1 cache RDY 0 = Busy 1 = Ready 5 ARDY ARDY2 ARDY ARDY2 ARDY Don't Care 4 – – – – – Don't Care 3 – – Rewrite recommended3 – – 0 = Normal or uncorrectable 1 = Rewrite recommended Block Erase Description Write protect 0 = Protected 1 = Not protected 2 – – – – – Don't Care 1 FAILC (N - 1) FAILC (N - 1) Reserved – – Don't Care FAIL (N) FAIL4 – FAIL 0 FAIL Notes: 0 = Successful PROGRAM/ ERASE/READ 1 = Error in PROGRAM/ ERASE/READ 1. Status register bit 6 is 1 when the cache is ready to accept new data. R/B# follows bit 6. 2. Status register bit 5 is 0 during the actual programming operation. If cache mode is used, this bit will be 1 when all internal operations are complete. 3. A status register bit defined as Rewrite Recommended signifies that the page includes acertain number of READ errors per sector (512B (main) + 4B (spare) + 8B (parity). A rewriteof this page is recommended. (Up to a 4-bit error has been corrected if internal ECC was enabled.) 4. A status register bit defined as FAIL signifies that an uncorrectable READ error has occurred. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 58 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Status Operations READ STATUS (70h) The READ STATUS (70h) command returns the status of the last-selected die (LUN) on a target. This command is accepted by the last-selected die (LUN) even when it is busy (RDY = 0). If there is only one die (LUN) per target, the READ STATUS (70h) command can be used to return status following any NAND command. In devices that have more than one die (LUN) per target, during and following interleaved die (multi-LUN) operations, the READ STATUS ENHANCED (78h) command must be used to select the die (LUN) that should report status. In this situation, using the READ STATUS (70h) command will result in bus contention, as two or more die (LUNs) could respond until the next operation is issued. The READ STATUS (70h) command can be used following all single-die (LUN) operations. Figure 33: READ STATUS (70h) Operation Cycle type Command DOUT tWHR I/O[7:0] 70h SR READ STATUS ENHANCED (78h) The READ STATUS ENHANCED (78h) command returns the status of the addressed die (LUN) on a target even when it is busy (RDY = 0). This command is accepted by all die (LUNs), even when they are BUSY (RDY = 0). Writing 78h to the command register, followed by three row address cycles containing the page, block, and LUN addresses, puts the selected die (LUN) into read status mode. The selected die (LUN) stays in this mode until another valid command is issued. Die (LUNs) that are not addressed are deselected to avoid bus contention. The selected LUN's status is returned when the host requests data output. The RDY and ARDY bits of the status register are shared for all planes on the selected die (LUN). The FAILC and FAIL bits are specific to the plane specified in the row address. The READ STATUS ENHANCED (78h) command also enables the selected die (LUN) for data output. To begin data output following a READ-series operation after the selected die (LUN) is ready (RDY = 1), issue the READ MODE (00h) command, then begin data output. If the host needs to change the cache register that will output data, use the RANDOM DATA READ TWO-PLANE (06h-E0h) command after the die (LUN) is ready. Use of the READ STATUS ENHANCED (78h) command is prohibited during the poweron RESET (FFh) command and when OTP mode is enabled. It is also prohibited following some of the other reset, identification, and configuration operations. See individual operations for specific details. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 59 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Status Operations Figure 34: READ STATUS ENHANCED (78h) Operation Cycle type Command Address Address Address DOUT tWHR I/Ox PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 78h R1 R2 60 R3 SR Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Column Address Operations Column Address Operations The column address operations affect how data is input to and output from the cache registers within the selected die (LUNs). These features provide host flexibility for managing data, especially when the host internal buffer is smaller than the number of data bytes or words in the cache register. When the asynchronous interface is active, column address operations can address any byte in the selected cache register. RANDOM DATA READ (05h-E0h) The RANDOM DATA READ (05h-E0h) command changes the column address of the selected cache register and enables data output from the last selected die (LUN). This command is accepted by the selected die (LUN) when it is ready (RDY = 1; ARDY = 1). It is also accepted by the selected die (LUN) during CACHE READ operations (RDY = 1; ARDY = 0). Writing 05h to the command register, followed by two column address cycles containing the column address, followed by the E0h command, puts the selected die (LUN) into data output mode. After the E0h command cycle is issued, the host must wait at least tWHR before requesting data output. The selected die (LUN) stays in data output mode until another valid command is issued. In devices with more than one die (LUN) per target, during and following interleaved die (multi-LUN) operations, the READ STATUS ENHANCED (78h) command must be issued prior to issuing the RANDOM DATA READ (05h-E0h). In this situation, using the RANDOM DATA READ (05h-E0h) command without the READ STATUS ENHANCED (78h) command will result in bus contention because two or more die (LUNs) could output data. Figure 35: RANDOM DATA READ (05h-E0h) Operation Cycle type DOUT DOUT Command Address Address Command tRHW I/O[7:0] Dn Dn + 1 DOUT DOUT DOUT Dk Dk + 1 Dk + 2 tWHR 05h C1 C2 E0h SR[6] PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 61 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Column Address Operations RANDOM DATA READ TWO-PLANE (06h-E0h) The RANDOM DATA READ TWO-PLANE (06h-E0h) command enables data output on the addressed die’s (LUN’s) cache register at the specified column address. This command is accepted by a die (LUN) when it is ready (RDY = 1; ARDY = 1). Writing 06h to the command register, followed by two column address cycles and three row address cycles, followed by E0h, enables data output mode on the address LUN’s cache register at the specified column address. After the E0h command cycle is issued, the host must wait at least tWHR before requesting data output. The selected die (LUN) stays in data output mode until another valid command is issued. Following a two-plane read page operation, the RANDOM DATA READ TWO-PLANE (06h-E0h) command is used to select the cache register to be enabled for data output. After data output is complete on the selected plane, the command can be issued again to begin data output on another plane. In devices with more than one die (LUN) per target, after all of the die (LUNs) on the target are ready (RDY = 1), the RANDOM DATA READ TWO-PLANE (06h-E0h) command can be used following an interleaved die (multi-LUN) read operation. Die (LUNs) that are not addressed are deselected to avoid bus contention. In devices with more than one die (LUN) per target, during interleaved die (multi-LUN) operations where more than one or more die (LUNs) are busy (RDY = 1; ARDY = 0 or RDY = 0; ARDY = 0), the READ STATUS ENHANCED (78h) command must be issued to the die (LUN) to be selected prior to issuing the RANDOM DATA READ TWO-PLANE (06h-E0h). In this situation, using the RANDOM DATA READ TWO-PLANE (06h-E0h) command without the READ STATUS ENHANCED (78h) command will result in bus contention, as two or more die (LUNs) could output data. If there is a need to update the column address without selecting a new cache register or LUN, the RANDOM DATA READ (05h-E0h) command can be used instead. Figure 36: RANDOM DATA READ TWO-PLANE (06h-E0h) Operation Cycle type DOUT DOUT Command Address Address Address Address Address Command tRHW I/O[7:0] Dn Dn + 1 DOUT DOUT DOUT Dk Dk + 1 Dk + 2 tWHR 06h PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 C1 C2 R1 R2 62 R3 E0h Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Column Address Operations RANDOM DATA INPUT (85h) The RANDOM DATA INPUT (85h) command changes the column address of the selected cache register and enables data input on the last-selected die (LUN). This command is accepted by the selected die (LUN) when it is ready (RDY = 1; ARDY = 1). It is also accepted by the selected die (LUN) during cache program operations (RDY = 1; ARDY = 0). Writing 85h to the command register, followed by two column address cycles containing the column address, puts the selected die (LUN) into data input mode. After the second address cycle is issued, the host must wait at least tADL before inputting data. The selected die (LUN) stays in data input mode until another valid command is issued. Though data input mode is enabled, data input from the host is optional. Data input begins at the column address specified. The RANDOM DATA INPUT (85h) command is allowed after the required address cycles are specified, but prior to the final command cycle (10h, 11h, 15h) of the following commands while data input is permitted: PROGRAM PAGE (80h-10h), PROGRAM PAGE CACHE (80h-15h), PROGRAM FOR INTERNAL DATA MOVE (85h-10h), and PROGRAM FOR TWO-PLANE INTERNAL DATA MOVE (85h-11h). In devices that have more than one die (LUN) per target, the RANDOM DATA INPUT (85h) command can be used with other commands that support interleaved die (multiLUN) operations. Figure 37: RANDOM DATA INPUT (85h) Operation As defined for PAGE (CACHE) PROGRAM Cycle type DIN DIN As defined for PAGE (CACHE) PROGRAM Command Address Address DIN DIN DIN Dk Dk + 1 Dk + 2 tADL I/O[7:0] Dn Dn + 1 85h C1 C2 RDY PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 63 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Column Address Operations PROGRAM FOR INTERNAL DATA INPUT (85h) The PROGRAM FOR INTERNAL DATA INPUT (85h) command changes the row address (block and page) where the cache register contents will be programmed in the NAND Flash array. It also changes the column address of the selected cache register and enables data input on the specified die (LUN). This command is accepted by the selected die (LUN) when it is ready (RDY = 1; ARDY = 1). It is also accepted by the selected die (LUN) during cache programming operations (RDY = 1; ARDY = 0). Write 85h to the command register. Then write two column address cycles and three row address cycles. This updates the page and block destination of the selected device for the addressed LUN and puts the cache register into data input mode. After the fifth address cycle is issued the host must wait at least tADL before inputting data. The selected LUN stays in data input mode until another valid command is issued. Though data input mode is enabled, data input from the host is optional. Data input begins at the column address specified. The PROGRAM FOR INTERNAL DATA INPUT (85h) command is allowed after the required address cycles are specified, but prior to the final command cycle (10h, 11h, 15h) of the following commands while data input is permitted: PROGRAM PAGE (80h-10h), PROGRAM PAGE TWO-PLANE (80h-11h), PROGRAM PAGE CACHE (80h-15h), PROGRAM FOR INTERNAL DATA MOVE (85h-10h), and PROGRAM FOR TWO-PLANE INTERNAL DATA MOVE (85h-11h). When used with these commands, the LUN address and plane select bits are required to be identical to the LUN address and plane select bits originally specified. The PROGRAM FOR INTERNAL DATA INPUT (85h) command enables the host to modify the original page and block address for the data in the cache register to a new page and block address. In devices that have more than one die (LUN) per target, the PROGRAM FOR INTERNAL DATA INPUT (85h) command can be used with other commands that support interleaved die (multi-LUN) operations. The PROGRAM FOR INTERNAL DATA INPUT (85h) command can be used with the RANDOM DATA READ (05h-E0h) or RANDOM DATA READ TWO-PLANE (06h-E0h) commands to read and modify cache register contents in small sections prior to programming cache register contents to the NAND Flash array. This capability can reduce the amount of buffer memory used in the host controller. The RANDOM DATA INPUT (85h) command can be used during the PROGRAM FOR INTERNAL DATA MOVE command sequence to modify one or more bytes of the original data. First, data is copied into the cache register using the 00h-35h command sequence, then the RANDOM DATA INPUT (85h) command is written along with the address of the data to be modified next. New data is input on the external data pins. This copies the new data into the cache register. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 64 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Column Address Operations Figure 38: PROGRAM FOR INTERNAL DATA INPUT (85h) Operation Cycle type DIN DIN Command Address Address Address Address Address Command DIN DIN DIN Dk Dk + 1 Dk + 2 tADL I/O[7:0] Dn Dn + 1 85h C1 C2 R1 R2 R3 10h RDY PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 65 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Read Operations Read Operations The READ PAGE (00h-30h) command, when issued by itself, reads one page from the NAND Flash array to its cache register and enables data output for that cache register. During data output the following commands can be used to read and modify the data in the cache registers: RANDOM DATA READ (05h-E0h) and RANDOM DATA INPUT (85h). Read Cache Operations To increase data throughput, the READ PAGE CACHE series (31h, 00h-31h) commands can be used to output data from the cache register while concurrently copying a page from the NAND Flash array to the data register. To begin a read page cache sequence, begin by reading a page from the NAND Flash array to its corresponding cache register using the READ PAGE (00h-30h) command. R/B# goes LOW during tR and the selected die (LUN) is busy (RDY = 0, ARDY = 0). After tR (R/B# is HIGH and RDY = 1, ARDY = 1), issue either of these commands: • READ PAGE CACHE SEQUENTIAL (31h) – copies the next sequential page from the NAND Flash array to the data register • READ PAGE CACHE RANDOM (00h-31h) – copies the page specified in this command from the NAND Flash array to its corresponding data register After the READ PAGE CACHE series (31h, 00h-31h) command has been issued, R/B# goes LOW on the target, and RDY = 0 and ARDY = 0 on the die (LUN) for tRCBSY while the next page begins copying data from the array to the data register. After tRCBSY, R/B# goes HIGH and the die’s (LUN’s) status register bits indicate the device is busy with a cache operation (RDY = 1, ARDY = 0). The cache register becomes available and the page requested in the READ PAGE CACHE operation is transferred to the data register. At this point, data can be output from the cache register, beginning at column address 0. The RANDOM DATA READ (05h-E0h) command can be used to change the column address of the data output by the die (LUN). After outputting the desired number of bytes from the cache register, either an additional READ PAGE CACHE series (31h, 00h-31h) operation can be started or the READ PAGE CACHE LAST (3Fh) command can be issued. If the READ PAGE CACHE LAST (3Fh) command is issued, R/B# goes LOW on the target, and RDY = 0 and ARDY = 0 on the die (LUN) for tRCBSY while the data register is copied into the cache register. After tRCBSY, R/B# goes HIGH and RDY = 1 and ARDY = 1, indicating that the cache register is available and that the die (LUN) is ready. Data can then be output from the cache register, beginning at column address 0. The RANDOM DATA READ (05h-E0h) command can be used to change the column address of the data being output. For READ PAGE CACHE series (31h, 00h-31h, 3Fh), during the die (LUN) busy time, tRCBSY, when RDY = 0 and ARDY = 0, the only valid commands are status operations (70h, 78h) and RESET (FFh). When RDY = 1 and ARDY = 0, the only valid commands during READ PAGE CACHE series (31h, 00h-31h) operations are status operations (70h, 78h), READ MODE (00h), READ PAGE CACHE series (31h, 00h-31h), RANDOM DATA READ (05h-E0h), and RESET (FFh). PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 66 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Read Operations Two-Plane Read Operations Two-plane read page operations improve data throughput by copying data from more than one plane simultaneously to the specified cache registers. This is done by prepending one or more READ PAGE TWO-PLANE (00h-00h-30h) commands in front of the READ PAGE (00h-30h) command. When the die (LUN) is ready, the RANDOM DATA READ TWO-PLANE (06h-E0h) command determines which plane outputs data. During data output, the following commands can be used to read and modify the data in the cache registers: RANDOM DATA READ (05h-E0h) and RANDOM DATA INPUT (85h). Two-Plane Read Cache Operations Two-plane read cache operations can be used to output data from more than one cache register while concurrently copying one or more pages from the NAND Flash array to the data register. This is done by prepending READ PAGE TWO-PLANE (00h-00h-30h) commands in front of the PAGE READ CACHE RANDOM (00h-31h) command. To begin a two-plane read page cache sequence, begin by issuing a READ PAGE TWOPLANE operation using the READ PAGE TWO-PLANE (00h-00h-30h) and READ PAGE (00h-30h) commands. R/B# goes LOW during tR and the selected die (LUN) is busy (RDY = 0, ARDY = 0). After tR (R/B# is HIGH and RDY = 1, ARDY = 1), issue either of these commands: • READ PAGE CACHE SEQUENTIAL (31h) – copies the next sequential pages from the previously addressed planes from the NAND Flash array to the data registers. • READ PAGE TWO-PLANE (00h-00h-30h) [in some cases, followed by READ PAGE CACHE RANDOM (00h-31h)] – copies the pages specified from the NAND Flash array to the corresponding data registers. After the READ PAGE CACHE series (31h, 00h-31h) command has been issued, R/B# goes LOW on the target, and RDY = 0 and ARDY = 0 on the die (LUN) for tRCBSY while the next pages begin copying data from the array to the data registers. After tRCBSY, R/B# goes HIGH and the LUN’s status register bits indicate the device is busy with a cache operation (RDY = 1, ARDY = 0). The cache registers become available and the pages requested in the READ PAGE CACHE operation are transferred to the data registers. Issue the RANDOM DATA READ TWO-PLANE (06h-E0h) command to determine which cache register will output data. After data is output, the RANDOM DATA READ TWOPLANE (06h-E0h) command can be used to output data from other cache registers. After a cache register has been selected, the RANDOM DATA READ (05h-E0h) command can be used to change the column address of the data output. After outputting data from the cache registers, either an additional TWO-PLANE READ CACHE series (31h, 00h-31h) operation can be started or the READ PAGE CACHE LAST (3Fh) command can be issued. If the READ PAGE CACHE LAST (3Fh) command is issued, R/B# goes LOW on the target, and RDY = 0 and ARDY = 0 on the die (LUN) for tRCBSY while the data registers are copied into the cache registers. After tRCBSY, R/B# goes HIGH and RDY = 1 and ARDY = 1, indicating that the cache registers are available and that the die (LUN) is ready. Issue the RANDOM DATA READ TWO-PLANE (06h-E0h) command to determine which cache register will output data. After data is output, the RANDOM DATA READ TWO-PLANE (06h-E0h) command can be used to output data from other cache registers. After a cache register has been selected, the RANDOM DATA READ (05h-E0h) command can be used to change the column address of the data output. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 67 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Read Operations For READ PAGE CACHE series (31h, 00h-31h, 3Fh), during the die (LUN) busy time, tRCBSY, when RDY = 0 and ARDY = 0, the only valid commands are status operations (70h, 78h) and RESET (FFh). When RDY = 1 and ARDY = 0, the only valid commands during READ PAGE CACHE series (31h, 00h-31h) operations are status operations (70h, 78h), READ MODE (00h), two-plane read cache series (31h, 00h-00h-30h, 00h-31h), RANDOM DATA READ (06h-E0h, 05h-E0h), and RESET (FFh). READ MODE (00h) The READ MODE (00h) command disables status output and enables data output for the last-selected die (LUN) and cache register after a READ operation (00h-30h, 00h-3Ah, 00h-35h) has been monitored with a status operation (70h, 78h). This command is accepted by the die (LUN) when it is ready (RDY = 1, ARDY = 1). It is also accepted by the die (LUN) during READ PAGE CACHE (31h, 00h-31h) operations (RDY = 1 and ARDY = 0). In devices that have more than one die (LUN) per target, during and following interleaved die (multi-LUN) operations, the READ STATUS ENHANCED (78h) command must be used to select only one die (LUN) prior to issuing the READ MODE (00h) command. This prevents bus contention. READ PAGE (00h-30h) The READ PAGE (00h–30h) command copies a page from the NAND Flash array to its respective cache register and enables data output. This command is accepted by the die (LUN) when it is ready (RDY = 1, ARDY = 1). To read a page from the NAND Flash array, write the 00h command to the command register, then write n address cycles to the address registers, and conclude with the 30h command. The selected die (LUN) will go busy (RDY = 0, ARDY = 0) for tR as data is transferred. To determine the progress of the data transfer, the host can monitor the target's R/B# signal or, alternatively, the status operations (70h, 78h) can be used. If the status operations are used to monitor the LUN's status, when the die (LUN) is ready (RDY = 1, ARDY = 1), the host disables status output and enables data output by issuing the READ MODE (00h) command. When the host requests data output, output begins at the column address specified. During data output the RANDOM DATA READ (05h-E0h) command can be issued. When internal ECC is enabled, the READ STATUS (70h) command is required after the completion of the data transfer (tR_ECC) to determine whether an uncorrectable read error occured. (tR_ECC is the data transferred with internal ECC enabled.) In devices that have more than one die (LUN) per target, during and following interleaved die (multi-LUN) operations the READ STATUS ENHANCED (78h) command must be used to select only one die (LUN) prior to the issue of the READ MODE (00h) command. This prevents bus contention. The READ PAGE (00h-30h) command is used as the final command of a two-plane read operation. It is preceded by one or more READ PAGE TWO-PLANE (00h-00h-30h) commands. Data is transferred from the NAND Flash array for all of the addressed planes to their respective cache registers. When the die (LUN) is ready (RDY = 1, ARDY = 1), data output is enabled for the cache register linked to the plane addressed in the READ PAGE (00h-30h) command. When the host requests data output, PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 68 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Read Operations output begins at the column address last specified in the READ PAGE (00h-30h) command. The RANDOM DATA READ TWO-PLANE (06h-E0h) command is used to enable data output in the other cache registers. Figure 39: READ PAGE (00h-30h) Operation Cycle type I/O[7:0] Command Address Address Address Address Address Command 00h C1 C2 R1 R2 R3 30h tWB tR DOUT DOUT DOUT Dn Dn+1 Dn+2 tRR RDY Figure 40: READ PAGE (00h-30h) Operation with Internal ECC Enabled tR_ECC RDY I/O[7:0] 00h Address Address Address Address Address 30h 70h Status 00h DOUT (serial access) SR bit 0 = 0 READ successful SR bit 1 = 0 READ error READ PAGE CACHE SEQUENTIAL (31h) The READ PAGE CACHE SEQUENTIAL (31h) command reads the next sequential page within a block into the data register while the previous page is output from the cache register. This command is accepted by the die (LUN) when it is ready (RDY = 1, ARDY = 1). It is also accepted by the die (LUN) during READ PAGE CACHE (31h, 00h-31h) operations (RDY = 1 and ARDY = 0). To issue this command, write 31h to the command register. After this command is issued, R/B# goes LOW and the die (LUN) is busy (RDY = 0, ARDY = 0) for tRCBSY. After tRCBSY, R/B# goes HIGH and the die (LUN) is busy with a cache operation (RDY = 1, ARDY = 0), indicating that the cache register is available and that the specified page is copying from the NAND Flash array to the data register. At this point, data can be output from the cache register beginning at column address 0. The RANDOM DATA READ (05h-E0h) command can be used to change the column address of the data being output from the cache register. The READ PAGE CACHE SEQUENTIAL (31h) command can be used to cross block boundaries. If the READ PAGE CACHE SEQUENTIAL (31h) command is issued after the last page of a block is read into the data register, the next page read will be the next logical block in which the 31h command was issued. Do not issue the READ PAGE CACHE SEQUENTIAL (31h) to cross die (LUN) boundaries. Instead, issue the READ PAGE CACHE LAST (3Fh) command. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 69 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Read Operations Figure 41: READ PAGE CACHE SEQUENTIAL (31h) Operation Cycle type I/O[7:0] Command Address x5 Command 00h Page Address M 30h tWB Command 31h tR RR tWB tRCBSY DOUT DOUT DOUT Command D0 … Dn 31h tWB tRR DOUT D0 tRCBSY tRR RDY Page M Page M+1 READ PAGE CACHE RANDOM (00h-31h) The READ PAGE CACHE RANDOM (00h-31h) command reads the specified block and page into the data register while the previous page is output from the cache register. This command is accepted by the die (LUN) when it is ready (RDY = 1, ARDY = 1). It is also accepted by the die (LUN) during READ PAGE CACHE (31h, 00h-31h) operations (RDY = 1 and ARDY = 0). To issue this command, write 00h to the command register, then write n address cycles to the address register, and conclude by writing 31h to the command register. The column address in the address specified is ignored. The die (LUN) address must match the same die (LUN) address as the previous READ PAGE (00h-30h) command or, if applicable, the previous READ PAGE CACHE RANDOM (00h-31h) command. After this command is issued, R/B# goes LOW and the die (LUN) is busy (RDY = 0, ARDY = 0) for tRCBSY. After tRCBSY, R/B# goes HIGH and the die (LUN) is busy with a cache operation (RDY = 1, ARDY = 0), indicating that the cache register is available and that the specified page is copying from the NAND Flash array to the data register. At this point, data can be output from the cache register beginning at column address 0. The RANDOM DATA READ (05h-E0h) command can be used to change the column address of the data being output from the cache register. In devices that have more than one die (LUN) per target, during and following interleaved die (multi-LUN) operations the READ STATUS ENHANCED (78h) command followed by the READ MODE (00h) command must be used to select only one die (LUN) and prevent bus contention. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 70 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Read Operations Figure 42: READ PAGE CACHE RANDOM (00h-31h) Operation Cycle type I/O[7:0] Command Address x5 Command 00h Page Address M 30h tWB tR Command Address x5 Command 00h Page Address N 31h tWB RR tRCBSY DOUT DOUT DOUT Command D0 … Dn 00h tRR RDY Page M 1 Cycle type I/O[7:0] DOUT Command Address x5 Command Dn 00h Page Address P 31h tWB DOUT D0 tRCBSY tRR RDY Page N 1 PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 71 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Read Operations READ PAGE CACHE LAST (3Fh) The READ PAGE CACHE LAST (3Fh) command ends the read page cache sequence and copies a page from the data register to the cache register. This command is accepted by the die (LUN) when it is ready (RDY = 1, ARDY = 1). It is also accepted by the die (LUN) during READ PAGE CACHE (31h, 00h-31h) operations (RDY = 1 and ARDY = 0). To issue the READ PAGE CACHE LAST (3Fh) command, write 3Fh to the command register. After this command is issued, R/B# goes LOW and the die (LUN) is busy (RDY = 0, ARDY = 0) for tRCBSY. After tRCBSY, R/B# goes HIGH and the die (LUN) is ready (RDY = 1, ARDY = 1). At this point, data can be output from the cache register, beginning at column address 0. The RANDOM DATA READ (05h-E0h) command can be used to change the column address of the data being output from the cache register. In devices that have more than one LUN per target, during and following interleaved die (multi-LUN) operations the READ STATUS ENHANCED (78h) command followed by the READ MODE (00h) command must be used to select only one die (LUN) and prevent bus contention. Figure 43: READ PAGE CACHE LAST (3Fh) Operation As defined for READ PAGE CACHE (SEQUENTIAL OR RANDOM) Cycle type I/O[7:0] Command 31h tWB tRCBSY DOUT DOUT DOUT Command D0 … Dn 3Fh tRR tWB tRCBSY DOUT DOUT DOUT D0 … Dn tRR RDY Page Address N PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 Page N 72 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Read Operations READ PAGE TWO-PLANE 00h-00h-30h The READ PAGE TWO-PLANE (00h-00h-30h) operation is similar to the PAGE READ (00h-30h) operation. It transfers two pages of data from the NAND Flash array to the data registers. Each page must be from a different plane on the same die. To enter the READ PAGE TWO-PLANE mode, write the 00h command to the command register, and then write five address cycles for plane 0 (BA6 = 0). Next, write the 00h command to the command register, and five address cycles for plane 1 (BA6 = 1). Finally, issue the 30h command. The first-plane and second-plane addresses must meet the two-plane addressing requirements, and, in addition, they must have identical column addresses. After the 30h command is written, page data is transferred from both planes to their respective data registers in tR. During these transfers, R/B# goes LOW. When the transfers are complete, R/B# goes HIGH. To read out the data from the plane 0 data register, pulse RE# repeatedly. After the data cycle from the plane 0 address completes, issue a RANDOM DATA READ TWO-PLANE (06h-E0h) command to select the plane 1 address, then repeatedly pulse RE# to read out the data from the plane 1 data register. Alternatively, the READ STATUS (70h) command can monitor data transfers. When the transfers are complete, status register bit 6 is set to 1. To read data from the first of the two planes, the user must first issue the RANDOM DATA READ TWO-PLANE (06h-E0h) command and pulse RE# repeatedly. When the data cycle is complete, issue a RANDOM DATA READ TWO-PLANE (06h-E0h) command to select the other plane. To output the data beginning at the specified column address, pulse RE# repeatedly. Use of the READ STATUS ENHANCED (78h) command is prohibited during and following a PAGE READ TWO-PLANE operation. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 73 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Read Operations Figure 44: READ PAGE TWO-PLANE (00h-00h-30h) Operation CLE WE# ALE RE# Page address M 00h I/Ox Col add 1 Col add 2 Row add 1 Column address J Row add 2 Page address M Row add 3 Col add 1 00h Col add 2 Row add 1 Column address J Plane 0 address Row add 2 Row add 3 30h tR Plane 1 address R/B# 1 CLE WE# ALE RE# I/Ox DOUT 0 DOUT 1 DOUT 06h Col add 1 Col add 2 Row add 1 Plane 0 data Row add 2 Row add 3 Plane 1 address E0h DOUT 0 DOUT 1 DOUT Plane 1 data R/B# 1 PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 74 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Program Operations Program Operations Program operations are used to move data from the cache or data registers to the NAND array. During a program operation the contents of the cache and/or data registers are modified by the internal control logic. Within a block, pages must be programmed sequentially from the least significant page address to the most significant page address (0, 1, 2, ….., 63). During a program operation, the contents of the cache and/or data registers are modified by the internal control logic. Program Operations The PROGRAM PAGE (80h-10h) command, when not preceded by the PROGRAM PAGE TWO-PLANE (80h-11h) command, programs one page from the cache register to the NAND Flash array. When the die (LUN) is ready (RDY = 1, ARDY = 1), the host should check the FAIL bit to verify that the operation has completed successfully. Program Cache Operations The PROGRAM PAGE CACHE (80h-15h) command can be used to improve program operation system performance. When this command is issued, the die (LUN) goes busy (RDY = 0, ARDY = 0) while the cache register contents are copied to the data register, and the die (LUN) is busy with a program cache operation (RDY = 1, ARDY = 0. While the contents of the data register are moved to the NAND Flash array, the cache register is available for an additional PROGRAM PAGE CACHE (80h-15h) or PROGRAM PAGE (80h-10h) command. For PROGRAM PAGE CACHE series (80h-15h) operations, during the die (LUN) busy times, tCBSY and tLPROG, when RDY = 0 and ARDY = 0, the only valid commands are status operations (70h, 78h) and reset (FFh). When RDY = 1 and ARDY = 0, the only valid commands during PROGRAM PAGE CACHE series (80h-15h) operations are status operations (70h, 78h), PROGRAM PAGE CACHE (80h-15h), PROGRAM PAGE (80h-10h), RANDOM DATA INPUT (85h), PROGRAM FOR INTERNAL DATA INPUT (85h), and RESET (FFh). Two-Plane Program Operations The PROGRAM PAGE TWO-PLANE (80h-11h) command can be used to improve program operation system performance by enabling multiple pages to be moved from the cache registers to different planes of the NAND Flash array. This is done by prepending one or more PROGRAM PAGE TWO-PLANE (80h-11h) commands in front of the PROGRAM PAGE (80h-10h) command. Two-Plane Program Cache Operations The PROGRAM PAGE TWO-PLANE (80h-11h) command can be used to improve program cache operation system performance by enabling multiple pages to be moved from the cache registers to the data registers and, while the pages are being transferred from the data registers to different planes of the NAND Flash array, free the cache registers to receive data input from the host. This is done by prepending one or more PROGRAM PAGE TWO-PLANE (80h-11h) commands in front of the PROGRAM PAGE CACHE (80h-15h) command. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 75 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Program Operations PROGRAM PAGE (80h-10h) The PROGRAM PAGE (80h-10h) command enables the host to input data to a cache register, and moves the data from the cache register to the specified block and page address in the array of the selected die (LUN). This command is accepted by the die (LUN) when it is ready (RDY = 1, ARDY = 1). It is also accepted by the die (LUN) when it is busy with a PROGRAM PAGE CACHE (80h-15h) operation (RDY = 1, ARDY = 0). To input a page to the cache register and move it to the NAND array at the block and page address specified, write 80h to the command register. Unless this command has been preceded by a PROGRAM PAGE TWO-PLANE (80h-11h) command, issuing the 80h to the command register clears all of the cache registers' contents on the selected target. Then write n address cycles containing the column address and row address. Data input cycles follow. Serial data is input beginning at the column address specified. At any time during the data input cycle the RANDOM DATA INPUT (85h) and PROGRAM FOR INTERNAL DATA INPUT (85h) commands may be issued. When data input is complete, write 10h to the command register. The selected LUN will go busy (RDY = 0, ARDY = 0) for tPROG as data is transferred. To determine the progress of the data transfer, the host can monitor the target's R/B# signal or, alternatively, the status operations (70h, 78h) may be used. When the die (LUN) is ready (RDY = 1, ARDY = 1), the host should check the status of the FAIL bit. In devices that have more than one die (LUN) per target, during and following interleaved die (multi-LUN) operations, the READ STATUS ENHANCED (78h) command must be used to select only one die (LUN) for status output. Use of the READ STATUS (70h) command could cause more than one die (LUN) to respond, resulting in bus contention. The PROGRAM PAGE (80h-10h) command is used as the final command of a two-plane program operation. It is preceded by one or more PROGRAM PAGE TWO-PLANE (80h-11h) commands. Data is transferred from the cache registers for all of the addressed planes to the NAND array. The host should check the status of the operation by using the status operations (70h, 78h). When internal ECC is enabled, the duration of array programming time is tPROG_ECC. During tPROG_ECC, the internal ECC generates parity bits when error detection is complete. Figure 45: PROGRAM PAGE (80h-10h) Operation Cycle type Command Address Address Address Address Address DIN DIN DIN DIN Command D0 D1 … Dn 10h Command DOUT 70h Status tADL I/O[7:0] 80h C1 C2 R1 R2 R3 tPROG tWB or tPROG_ECC RDY PROGRAM PAGE CACHE (80h-15h) The PROGRAM PAGE CACHE (80h-15h) command enables the host to input data to a cache register; copies the data from the cache register to the data register; then moves the data register contents to the specified block and page address in the array of the selected die (LUN). After the data is copied to the data register, the cache register is availa- PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 76 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Program Operations ble for additional PROGRAM PAGE CACHE (80h-15h) or PROGRAM PAGE (80h-10h) commands. The PROGRAM PAGE CACHE (80h-15h) command is accepted by the die (LUN) when it is ready (RDY =1, ARDY = 1). It is also accepted by the die (LUN) when busy with a PROGRAM PAGE CACHE (80h-15h) operation (RDY = 1, ARDY = 0). To input a page to the cache register to move it to the NAND array at the block and page address specified, write 80h to the command register. Unless this command has been preceded by a PROGRAM PAGE TWO-PLANE (80h-11h) command, issuing the 80h to the command register clears all of the cache registers' contents on the selected target. Then write n address cycles containing the column address and row address. Data input cycles follow. Serial data is input beginning at the column address specified. At any time during the data input cycle the RANDOM DATA INPUT (85h) and PROGRAM FOR INTERNAL DATA INPUT (85h) commands may be issued. When data input is complete, write 15h to the command register. The selected LUN will go busy (RDY = 0, ARDY = 0) for tCBSY to allow the data register to become available from a previous program cache operation, to copy data from the cache register to the data register, and then to begin moving the data register contents to the specified page and block address. To determine the progress of tCBSY, the host can monitor the target's R/B# signal or, alternatively, the status operations (70h, 78h) can be used. When the LUN’s status shows that it is busy with a PROGRAM CACHE operation (RDY = 1, ARDY = 0), the host should check the status of the FAILC bit to see if a previous cache operation was successful. If, after tCBSY, the host wants to wait for the program cache operation to complete, without issuing the PROGRAM PAGE (80h-10h) command, the host should monitor ARDY until it is 1. The host should then check the status of the FAIL and FAILC bits. In devices with more than one die (LUN) per target, during and following interleaved die (multi-LUN) operations, the READ STATUS ENHANCED (78h) command must be used to select only one die (LUN) for status output. Use of the READ STATUS (70h) command could cause more than one die (LUN) to respond, resulting in bus contention. The PROGRAM PAGE CACHE (80h-15h) command is used as the final command of a two-plane program cache operation. It is preceded by one or more PROGRAM PAGE TWO-PLANE (80h-11h) commands. Data for all of the addressed planes is transferred from the cache registers to the corresponding data registers, then moved to the NAND Flash array. The host should check the status of the operation by using the status operations (70h, 78h). PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 77 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Program Operations Figure 46: PROGRAM PAGE CACHE (80h–15h) Operation (Start) Cycle type Command Address Address Address Address Address DIN DIN DIN DIN Command D0 D1 … Dn 15h tADL I/O[7:0] 80h C1 C2 R1 R2 R3 tWB tCBSY RDY 1 Cycle type Command Address Address Address Address Address DIN DIN DIN DIN Command D0 D1 … Dn 15h tADL I/O[7:0] 80h C1 C2 R1 R2 R3 tWB tCBSY RDY 1 Figure 47: PROGRAM PAGE CACHE (80h–15h) Operation (End) As defined for PAGE CACHE PROGRAM Cycle type Command Address Address Address Address Address DIN DIN DIN DIN Command D0 D1 … Dn 15h tADL I/O[7:0] 80h C1 C2 R1 R2 R3 tWB tCBSY RDY 1 Cycle type Command Address Address Address Address Address DIN DIN DIN DIN Command D0 D1 … Dn 10h tADL I/O[7:0] 80h C1 C2 R1 R2 R3 tWB tLPROG RDY 1 PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 78 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Program Operations PROGRAM PAGE TWO-PLANE (80h-11h) The PROGRAM PAGE TWO-PLANE (80h-11h) command enables the host to input data to the addressed plane's cache register and queue the cache register to ultimately be moved to the NAND Flash array. This command can be issued one or more times. Each time a new plane address is specified that plane is also queued for data transfer. To input data for the final plane and to begin the program operation for all previously queued planes, issue either the PROGRAM PAGE (80h-10h) command or the PROGRAM PAGE CACHE (80h-15h) command. All of the queued planes will move the data to the NAND Flash array. This command is accepted by the die (LUN) when it is ready (RDY = 1). To input a page to the cache register and queue it to be moved to the NAND Flash array at the block and page address specified, write 80h to the command register. Unless this command has been preceded by a PROGRAM PAGE TWO-PLANE (80h-11h) command, issuing the 80h to the command register clears all of the cache registers' contents on the selected target. Write five address cycles containing the column address and row address; data input cycles follow. Serial data is input beginning at the column address specified. At any time during the data input cycle, the RANDOM DATA INPUT (85h) and PROGRAM FOR INTERNAL DATA INPUT (85h) commands can be issued. When data input is complete, write 11h to the command register. The selected die (LUN) will go busy (RDY = 0, ARDY = 0) for tDBSY. To determine the progress of tDBSY, the host can monitor the target's R/B# signal or, alternatively, the status operations (70h, 78h) can be used. When the LUN's status shows that it is ready (RDY = 1), additional PROGRAM PAGE TWO-PLANE (80h-11h) commands can be issued to queue additional planes for data transfer. Alternatively, the PROGRAM PAGE (80h-10h) or PROGRAM PAGE CACHE (80h-15h) commands can be issued. When the PROGRAM PAGE (80h-10h) command is used as the final command of a twoplane program operation, data is transferred from the cache registers to the NAND Flash array for all of the addressed planes during tPROG. When the die (LUN) is ready (RDY = 1, ARDY = 1), the host should check the status of the FAIL bit for each of the planes to verify that programming completed successfully. When the PROGRAM PAGE CACHE (80h-15h) command is used as the final command of a program cache two-plane operation, data is transferred from the cache registers to the data registers after the previous array operations finish. The data is then moved from the data registers to the NAND Flash array for all of the addressed planes. This occurs during tCBSY. After tCBSY, the host should check the status of the FAILC bit for each of the planes from the previous program cache operation, if any, to verify that programming completed successfully. For the PROGRAM PAGE TWO-PLANE (80h-11h), PROGRAM PAGE (80h-10h), and PROGRAM PAGE CACHE (80h-15h) commands, see Two-Plane Operations for two-plane addressing requirements. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 79 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Program Operations Figure 48: PROGRAM PAGE TWO-PLANE (80h–11h) Operation Cycle type Command Address Address Address Address Address DIN DIN DIN Command Command Address D0 … Dn 11h 80h ... tADL I/O[7:0] 80h C1 C2 R1 R2 R3 tWB tDBSY RDY PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 80 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Erase Operations Erase Operations Erase operations are used to clear the contents of a block in the NAND Flash array to prepare its pages for program operations. Erase Operations The ERASE BLOCK (60h-D0h) command, when not preceded by the ERASE BLOCK TWO-PLANE (60h-D1h) command, erases one block in the NAND Flash array. When the die (LUN) is ready (RDY = 1, ARDY = 1), the host should check the FAIL bit to verify that this operation completed successfully. TWO-PLANE ERASE Operations The ERASE BLOCK TWO-PLANE (60h-D1h) command can be used to further system performance of erase operations by allowing more than one block to be erased in the NAND array. This is done by prepending one or more ERASE BLOCK TWO-PLANE (60hD1h) commands in front of the ERASE BLOCK (60h-D0h) command. See Two-Plane Operations for details. ERASE BLOCK (60h-D0h) The ERASE BLOCK (60h-D0h) command erases the specified block in the NAND Flash array. This command is accepted by the die (LUN) when it is ready (RDY = 1, ARDY = 1). To erase a block, write 60h to the command register. Then write three address cycles containing the row address; the page address is ignored. Conclude by writing D0h to the command register. The selected die (LUN) will go busy (RDY = 0, ARDY = 0) for tBERS while the block is erased. To determine the progress of an ERASE operation, the host can monitor the target's R/B# signal, or alternatively, the status operations (70h, 78h) can be used. When the die (LUN) is ready (RDY = 1, ARDY = 1) the host should check the status of the FAIL bit. In devices that have more than one die (LUN) per target, during and following interleaved die (multi-LUN) operations, the READ STATUS ENHANCED (78h) command must be used to select only one die (LUN) for status output. Use of the READ STATUS (70h) command could cause more than one die (LUN) to respond, resulting in bus contention. The ERASE BLOCK (60h-D0h) command is used as the final command of an erase twoplane operation. It is preceded by one or more ERASE BLOCK TWO-PLANE (60h-D1h) commands. All blocks in the addressed planes are erased. The host should check the status of the operation by using the status operations (70h, 78h). See Two-Plane Operations for two-plane addressing requirements. Figure 49: ERASE BLOCK (60h-D0h) Operation Cycle type I/O[7:0] Command Address Address Address Command 60h R1 R2 R3 D0h tWB tBERS RDY PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 81 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Erase Operations ERASE BLOCK TWO-PLANE (60h-D1h) The ERASE BLOCK TWO-PLANE (60h-D1h) command queues a block in the specified plane to be erased in the NAND Flash array. This command can be issued one or more times. Each time a new plane address is specified, that plane is also queued for a block to be erased. To specify the final block to be erased and to begin the ERASE operation for all previously queued planes, issue the ERASE BLOCK (60h-D0h) command. This command is accepted by the die (LUN) when it is ready (RDY = 1, ARDY = 1). To queue a block to be erased, write 60h to the command register, then write three address cycles containing the row address; the page address is ignored. Conclude by writing D1h to the command register. The selected die (LUN) will go busy (RDY = 0, ARDY = 0) for tDBSY. To determine the progress of tDBSY, the host can monitor the target's R/B# signal, or alternatively, the status operations (70h, 78h) can be used. When the LUN's status shows that it is ready (RDY = 1, ARDY = 1), additional ERASE BLOCK TWO-PLANE (60hD1h) commands can be issued to queue additional planes for erase. Alternatively, the ERASE BLOCK (60h-D0h) command can be issued to erase all of the queued blocks. For two-plane addressing requirements for the ERASE BLOCK TWO-PLANE (60h-D1h) and ERASE BLOCK (60h-D0h) commands, see Two-Plane Operations. Figure 50: ERASE BLOCK TWO-PLANE (60h–D1h) Operation Cycle type I/O[7:0] Command Address Address Address Command 60h R1 R2 R3 D1h tWB Command Address 60h ... tDBSY RDY PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 82 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Internal Data Move Operations Internal Data Move Operations Internal data move operations make it possible to transfer data within a device from one page to another using the cache register. This is particularly useful for block management and wear leveling. The INTERNAL DATA MOVE operation is a two-step process consisting of a READ FOR INTERNAL DATA MOVE (00h-35h) and a PROGRAM FOR INTERNAL DATA MOVE (85h-10h) command. To move data from one page to another on the same plane, first issue the READ FOR INTERNAL DATA MOVE (00h-35h) command. When the die (LUN) is ready (RDY = 1, ARDY = 1), the host can transfer the data to a new page by issuing the PROGRAM FOR INTERNAL DATA MOVE (85h-10h) command. When the die (LUN) is again ready (RDY = 1, ARDY = 1), the host should check the FAIL bit to verify that this operation completed successfully. To prevent bit errors from accumulating over multiple INTERNAL DATA MOVE operations, it is recommended that the host read the data out of the cache register after the READ FOR INTERNAL DATA MOVE (00h-35h) completes and prior to issuing the PROGRAM FOR INTERNAL DATA MOVE (85h-10h) command. The RANDOM DATA READ (05h-E0h) command can be used to change the column address. The host should check the data for ECC errors and correct them. When the PROGRAM FOR INTERNAL DATA MOVE (85h-10h) command is issued, any corrected data can be input. The PROGRAM FOR INTERNAL DATA INPUT (85h) command can be used to change the column address. It is not possible to use the READ FOR INTERNAL DATA MOVE operation to move data from one plane to another or from one die (LUN) to another. Instead, use a READ PAGE (00h-30h) or READ FOR INTERNAL DATA MOVE (00h-35h) command to read the data out of the NAND, and then use a PROGRAM PAGE (80h-10h) command with data input to program the data to a new plane or die (LUN). Between the READ FOR INTERNAL DATA MOVE (00h-35h) and PROGRAM FOR INTERNAL DATA MOVE (85h-10h) commands, the following commands are supported: status operations (70h, 78h) and column address operations (05h-E0h, 06h-E0h, 85h). The RESET operation (FFh) can be issued after READ FOR INTERNAL DATA MOVE (00h-35h), but the contents of the cache registers on the target are not valid. In devices that have more than one die (LUN) per target, once the READ FOR INTERNAL DATA MOVE (00h-35h) is issued, interleaved die (multi-LUN) operations are prohibited until after the PROGRAM FOR INTERNAL DATA MOVE (85h-10h) command is issued. Two-Plane Read for Internal Data Move Operations Two-plane internal data move read operations improve read data throughput by copying data simultaneously from more than one plane to the specified cache registers. This is done by issuing the READ PAGE TWO-PLANE (00h-00h-30h) command or the READ FOR INTERNAL DATA MOVE (00h-00h-35h) command. The INTERNAL DATA MOVE PROGRAM TWO-PLANE (85h-11h) command can be used to further system performance of PROGRAM FOR INTERNAL DATA MOVE operations by enabling movement of multiple pages from the cache registers to different planes of the NAND Flash array. This is done by prepending one or more PROGRAM FOR INTERNAL DATA MOVE (85h-11h) commands in front of the PROGRAM FOR INTERNAL DATA MOVE (85h-10h) command. See Two-Plane Operations for details. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 83 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Internal Data Move Operations READ FOR INTERNAL DATA MOVE (00h-35h) The READ FOR INTERNAL DATA MOVE (00h-35h) command is functionally identical to the READ PAGE (00h-30h) command, except that 35h is written to the command register instead of 30h. Though it is not required, it is recommended that the host read the data out of the device to verify the data prior to issuing the PROGRAM FOR INTERNAL DATA MOVE (85h-10h) command to prevent the propagation of data errors. If internal ECC is enabled, the data does not need to be toggled out by the host to be corrected and moving data can then be written to a new page without data reloading, which improves system performance. Figure 51: READ FOR INTERNAL DATA MOVE (00h-35h) Operation Cycle type Command Address Address Address Address Address Command 00h C1 C2 R1 R2 R3 35h I/O[7:0] tWB tR DOUT DOUT DOUT Dn Dn+1 Dn+2 tRR RDY Figure 52: READ FOR INTERNAL DATA MOVE (00h–35h) with RANDOM DATA READ (05h–E0h) Cycle type I/O[7:0] Command Address Address Address Address Address Command 00h C1 C2 R1 R2 R3 35h tWB tR DOUT DOUT DOUT D0 … Dj + n tRR RDY 1 Cycle type Command Address Address Command DOUT DOUT DOUT Dk Dk + 1 Dk + 2 tWHR I/O[7:0] 05h C1 C2 E0h RDY 1 PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 84 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Internal Data Move Operations Figure 53: INTERNAL DATA MOVE (85h-10h) with Internal ECC Enabled tR_ECC tPROG_ECC R/B# I/O[7:0] 00h Address (5 cycles) 35h 70h Source address Status DOUT 00h SR bit 0 = 0 READ successful SR bit 1 = 0 READ error 85h Address (5 cycles) 10h 70h Destination address DOUT is optional Status 00h SR bit 0 = 0 READ successful SR bit 1 = 0 READ error Figure 54: INTERNAL DATA MOVE (85h-10h) with RANDOM DATA INPUT with Internal ECC Enabled tR_ECC tPROG_ECC R/B# I/O[7:0] 00h Address (5 cycles) 35h Source address 70h Status DOUT 00h SR bit 0 = 0 READ successful SR bit 1 = 0 READ error Address (5 cycles) Data 85h 85h DOUT is optional Address (2 cycles) Data 10h 70h Destination address Column address 1, 2 (Unlimitted repetitions are possible) PROGRAM FOR INTERNAL DATA MOVE (85h–10h) The PROGRAM FOR INTERNAL DATA MOVE (85h-10h) command is functionally identical to the PROGRAM PAGE (80h-10h) command, except that when 85h is written to the command register, cache register contents are not cleared. Figure 55: PROGRAM FOR INTERNAL DATA MOVE (85h–10h) Operation Cycle type I/O[7:0] Command Address Address Address Address Address Command 85h C1 C2 R1 R2 R3 10h tWB tPROG RDY PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 85 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Internal Data Move Operations Figure 56: PROGRAM FOR INTERNAL DATA MOVE (85h-10h) with RANDOM DATA INPUT (85h) Cycle type Command Address Address Address Address Address DIN DIN Di Di + 1 tWHR I/O[7:0] 85h C1 C2 R1 R2 R3 RDY 1 Cycle type Command Address Address DIN DIN DIN Command Dj Dj + 1 Dj + 2 10h tWHR I/O[7:0] 85h C1 C2 tWB tPROG RDY 1 PROGRAM FOR INTERNAL DATA MOVE TWO-PLANE (85h-11h) The PROGRAM FOR INTERNAL DATA MOVE TWO-PLANE (85h-11h) command is functionally identical to the PROGRAM PAGE TWO-PLANE (85h-11h) command, except that when 85h is written to the command register, cache register contents are not cleared. See Program Operations for further details. Figure 57: PROGRAM FOR INTERNAL DATA MOVE TWO-PLANE (85h-11h) Operation Cycle type Command Address Address Address Address Address DIN DIN DIN Command Command Address D0 … Dn 11h 85h ... tADL I/O[7:0] 85h C1 C2 R1 R2 R3 tWB tDBSY RDY PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 86 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Block Lock Feature Block Lock Feature The block lock feature protects either the entire device or ranges of blocks from being programmed and erased. Using the block lock feature is preferable to using WP# to prevent PROGRAM and ERASE operations. Block lock is enabled and disabled at power-on through the LOCK pin. At power-on, if LOCK is LOW, all BLOCK LOCK commands are disabled. However if LOCK is HIGH at power-on, the BLOCK LOCK commands are enabled and, by default, all the blocks on the device are protected, or locked, from PROGRAM and ERASE operations, even if WP# is HIGH. Before the contents of the device can be modified, the device must first be unlocked. Either a range of blocks or the entire device may be unlocked. PROGRAM and ERASE operations complete successfully only in the block ranges that have been unlocked. Blocks, once unlocked, can be locked again to protect them from further PROGRAM and ERASE operations. Blocks that are locked can be protected further, or locked tight. When locked tight, the device’s blocks can no longer be locked or unlocked until the device is power cycled. WP# and Block Lock The following is true when the block lock feature is enabled: • Holding WP# LOW locks all blocks, provided the blocks are not locked tight. • If WP# is held LOW to lock blocks, then returned to HIGH, a new UNLOCK command must be issued to unlock blocks. UNLOCK (23h-24h) By default at power-on, if LOCK is HIGH, all the blocks are locked and protected from PROGRAM and ERASE operations. The UNLOCK (23h) command is used to unlock a range of blocks. Unlocked blocks have no protection and can be programmed or erased. The UNLOCK command uses two registers, a lower boundary block address register and an upper boundary block address register, and the invert area bit to determine what range of blocks are unlocked. When the invert area bit = 0, the range of blocks within the lower and upper boundary address registers are unlocked. When the invert area bit = 1, the range of blocks outside the boundaries of the lower and upper boundary address registers are unlocked. The lower boundary block address must be less than the upper boundary block address. The figures below show examples of how the lower and upper boundary address registers work with the invert area bit. To unlock a range of blocks, issue the UNLOCK (23h) command followed by the appropriate address cycles that indicate the lower boundary block address. Then issue the 24h command followed by the appropriate address cycles that indicate the upper boundary block address. The least significant page address bit, PA0, should be set to 1 if setting the invert area bit; otherwise, it should be 0. The other page address bits should be 0. Only one range of blocks can be specified in the lower and upper boundary block address registers. If after unlocking a range of blocks the UNLOCK command is again issued, the new block address range determines which blocks are unlocked. The previous unlocked block address range is not retained. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 87 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Block Lock Feature Figure 58: Flash Array Protected: Invert Area Bit = 0 Block 4095 Block 4094 Block 4093 Block 4092 Block 4091 Block 4090 Block 4089 Block 4088 Block. 4087 .. .. .. .. .. .. . Block 0002 Block 0001 Block 0000 Protected area FFCh Upper block boundary FF8h Lower block boundary Unprotected area Protected area Figure 59: Flash Array Protected: Invert Area Bit = 1 Block 4095 Block 4094 Block 4093 Block 4092 Block 4091 Block 4090 Block 4089 Block 4088 Block. 4087 .. .. .. .. .. .. . Block 0002 Block 0001 Block 0000 PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 Unprotected Area FFCh Upper block boundary FF8h Lower block boundary Protected area Unprotected area 88 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Block Lock Feature Table 22: Block Lock Address Cycle Assignments I/O[15:8]1 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 First LOW BA7 BA6 LOW LOW LOW LOW LOW Invert area bit2 Second LOW BA15 BA14 BA13 BA12 BA11 BA10 BA9 BA8 Third LOW LOW LOW LOW LOW LOW LOW BA17 BA16 ALE Cycle Notes: 1. I/O[15:8] is applicable only for x16 devices. 2. Invert area bit is applicable for 24h command; it may be LOW or HIGH for 23h command. Figure 60: UNLOCK Operation WP# CLE CE# WE# ALE RE# I/Ox 23h Unlock Block Block Block add 1 add 2 add 3 Lower boundary 24h Block Block Block add 1 add 2 add 3 Upper boundary R/B# PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 89 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Block Lock Feature LOCK (2Ah) By default at power-on, if LOCK is HIGH, all the blocks are locked and protected from PROGRAM and ERASE operations. If portions of the device are unlocked using the UNLOCK (23h) command, they can be locked again using the LOCK (2Ah) command. The LOCK command locks all of the blocks in the device. Locked blocks are write-protected from PROGRAM and ERASE operations. To lock all of the blocks in the device, issue the LOCK (2Ah) command. When a PROGRAM or ERASE operation is issued to a locked block, R/B# goes LOW for tLBSY. The PROGRAM or ERASE operation does not complete. Any READ STATUS command reports bit 7 as 0, indicating that the block is protected. The LOCK (2Ah) command is disabled if LOCK is LOW at power-on or if the device is locked tight. Figure 61: LOCK Operation CLE CE# WE# I/Ox 2Ah LOCK command PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 90 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Block Lock Feature LOCK TIGHT (2Ch) The LOCK TIGHT (2Ch) command prevents locked blocks from being unlocked and also prevents unlocked blocks from being locked. When this command is issued, the UNLOCK (23h) and LOCK (2Ah) commands are disabled. This provides an additional level of protection against inadvertent PROGRAM and ERASE operations to locked blocks. To implement LOCK TIGHT in all of the locked blocks in the device, verify that WP# is HIGH and then issue the LOCK TIGHT (2Ch) command. When a PROGRAM or ERASE operation is issued to a locked block that has also been locked tight, R/B# goes LOW for tLBSY. The PROGRAM or ERASE operation does not complete. The READ STATUS (70h) command reports bit 7 as 0, indicating that the block is protected. PROGRAM and ERASE operations complete successfully to blocks that were not locked at the time the LOCK TIGHT command was issued. After the LOCK TIGHT command is issued, the command cannot be disabled via a software command. The only ways to disable the lock tight status is to power cycle the device. When the lock tight status is disabled, all of the blocks become locked, the same as if the LOCK (2Ah) command had been issued. The LOCK TIGHT (2Ch) command is disabled if LOCK is LOW at power-on. Figure 62: LOCK TIGHT Operation LOCK WP# CLE CE# WE# I/Ox 2Ch LOCK TIGHT command R/B# PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 91 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Block Lock Feature Figure 63: PROGRAM/ERASE Issued to Locked Block t LBSY R/B# I/Ox PROGRAM or ERASE Add ress/data input CONFIRM 70h Locked block 60h READ STATUS BLOCK LOCK READ STATUS (7Ah) The BLOCK LOCK READ STATUS (7Ah) command is used to determine the protection status of individual blocks. The address cycles have the same format, as shown below, and the invert area bit should be set LOW. On the falling edge of RE# the I/O pins output the block lock status register, which contains the information on the protection status of the block. Table 23: Block Lock Status Register Bit Definitions Block Lock Status Register Definitions I/O[7:3] I/O2 (Lock#) I/O1 (LT#) I/O0 (LT) Block is locked tight X 0 0 1 Block is locked X 0 1 0 Block is unlocked, and device is locked tight X 1 0 1 Block is unlocked, and device is not locked tight X 1 1 0 Figure 64: BLOCK LOCK READ STATUS CLE CE# WE# tWHR ALE RE# I/Ox 7Ah BLOCK LOCK READ STATUS PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 Add 1 Add 2 Add 3 Status Block address 92 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Block Lock Feature Figure 65: BLOCK LOCK Flowchart Power-up Power-up with LOCK HIGH Power-up with LOCK LOW (default) Entire NAND Flash array locked BLOCK LOCK function disabled LOCK TIGHT Cmd with WP# and LOCK HIGH Entire NAND Flash array locked tight UNLOCK Cmd with invert area bit = 1 UNLOCK Cmd with invert area bit = 0 WP# LOW >100ns or LOCK Cmd WP# LOW >100ns or LOCK Cmd Unlocked range Locked range Locked range Unlocked range UNLOCK Cmd with invert area bit = 0 UNLOCK Cmd with invert area bit = 1 Unlocked range UNLOCK Cmd with invert area bit = 1 UNLOCK Cmd with invert area bit = 0 Locked range LOCK TIGHT Cmd with WP# and LOCK HIGH LOCK TIGHT Cmd with WP# and LOCK HIGH Unlocked range Locked tight range Locked tight range Unlocked range Unlocked range Locked-tight range PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 93 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP One-Time Programmable (OTP) Operations One-Time Programmable (OTP) Operations This Micron NAND Flash device offers a protected, one-time programmable NAND Flash memory area. Thirty full pages (2112 bytes per page) of OTP data are available on the device, and the entire range is guaranteed to be good. The OTP area is accessible only through the OTP commands. Customers can use the OTP area any way they choose; typical uses include programming serial numbers or other data for permanent storage. The OTP area leaves the factory in an unwritten state (all bits are 1s). Programming or partial-page programming enables the user to program only 0 bits in the OTP area. The OTP area cannot be erased, whether it is protected or not. Protecting the OTP area prevents further programming of that area. Micron provides a unique way to program and verify data before permanently protecting it and preventing future changes. The OTP area is only accessible while in OTP operation mode. To set the device to OTP operation mode, issue the SET FEATURE (EFh) command to feature address 90h and write 01h to P1, followed by three cycles of 00h to P2-P4. For parameters to enter OTP mode, see Features Operations. When the device is in OTP operation mode, all subsequent PAGE READ (00h-30h) and PROGRAM PAGE (80h-10h) commands are applied to the OTP area. The OTP area is assigned to page addresses 02h-1Fh. To program an OTP page, issue the PROGRAM PAGE (80h-10h) command. The pages must be programmed in the ascending order. Similarly, to read an OTP page, issue the PAGE READ (00h-30h) command. Protecting the OTP is done by entering OTP protect mode. To set the device to OTP protect mode, issue the SET FEATURE (EFh) command to feature address 90h and write 03h to P1, followed by three cycles of 00h to P2-P4. To determine whether the device is busy during an OTP operation, either monitor R/B# or use the READ STATUS (70h) command. To exit OTP operation or protect mode, write 00h to P1 at feature address 90h. Legacy OTP Commands For legacy OTP commands, OTP DATA PROGRAM (A0h-10h), OTP DATA PROTECT (A5h-10h), and OTP DATA READ (AFh-30h), refer to the MT29F4GxxAxC data sheet. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 94 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP One-Time Programmable (OTP) Operations OTP DATA PROGRAM (80h-10h) The OTP DATA PROGRAM (80h-10h) command is used to write data to the pages within the OTP area. An entire page can be programmed at one time, or a page can be partially programmed up to eight times. Only the OTP area allows up to eight partial-page programs. The rest of the blocks support only four partial-page programs. There is no ERASE operation for OTP pages. PROGRAM PAGE enables programming into an offset of an OTP page using two bytes of the column address (CA[12:0]). The command is compatible with the RANDOM DATA INPUT (85h) command. The PROGRAM PAGE command will not execute if the OTP area has been protected. To use the PROGRAM PAGE command, issue the 80h command. Issue n address cycles. The first two address cycles are the column address. For the remaining cycles, select a page in the range of 02h-00h through 1Fh-00h. Next, write from 1–2112 bytes of data. After data input is complete, issue the 10h command. The internal control logic automatically executes the proper programming algorithm and controls the necessary timing for programming and verification. R/B# goes LOW for the duration of the array programming time (tPROG). The READ STATUS (70h) command is the only valid command for reading status in OTP operation mode. Bit 5 of the status register reflects the state of R/B#. When the device is ready, read bit 0 of the status register to determine whether the operation passed or failed (see Status Operations). Each OTP page can be programmed to 8 partial-page programming. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 95 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP One-Time Programmable (OTP) Operations RANDOM DATA INPUT (85h) After the initial OTP data set is input, additional data can be written to a new column address with the RANDOM DATA INPUT (85h) command. The RANDOM DATA INPUT command can be used any number of times in the same page prior to the OTP PAGE WRITE (10h) command being issued. Figure 66: OTP DATA PROGRAM (After Entering OTP Operation Mode) CLE CE# tWC WE# tWB tPROG ALE RE# I/Ox Col add 1 80h Col add 2 OTP DATA INPUT command OTP page1 OTP address1 00h 00h DIN n DIN m 1 up to m bytes serial input 10h 70h PROGRAM command READ STATUS command Status R/B# x8 device: m = 2112 bytes x16 device: m = 1056 words OTP data written (following good status confirmation) Don’t Care Note: 1. The OTP page must be within the 02h–1Fh range. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 96 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP One-Time Programmable (OTP) Operations Figure 67: OTP DATA PROGRAM Operation with RANDOM DATA INPUT (After Entering OTP Operation Mode) CLE CE# tWC tADL tADL WE# tWB tPROG ALE RE# I/Ox 80h Col add1 OTP Col add2 page1 00h 00h SERIAL DATA INPUT command DIN Col Col 85h add1 add2 n+1 Serial input RANDOM DATA Column address INPUT command DIN n DIN 10h n+1 Serial input PROGRAM command DIN n 70h Status READ STATUS command R/B# Don‘t Care OTP DATA PROTECT (80h-10) The OTP DATA PROTECT (80h-10h) command is used to prevent further programming of the pages in the OTP area. To protect the OTP area, the target must be in OTP operation mode. To protect all data in the OTP area, issue the 80h command. Issue n address cycles including the column address, OTP protect page address and block address; the column and block addresses are fixed to 0. Next, write 00h data for the first byte location and issue the 10h command. R/B# goes LOW for the duration of the array programming time, tPROG. After the data is protected, it cannot be programmed further. When the OTP area is protected, the pages within the area are no longer programmable and cannot be unprotected. The READ STATUS (70h) command is the only valid command for reading status in OTP operation mode. The RDY bit of the status register will reflect the state of R/B#. Use of the READ STATUS ENHANCED (78h) command is prohibited. When the target is ready, read the FAIL bit of the status register to determine if the operation passed or failed. If the OTP DATA PROTECT (80h-10h) command is issued after the OTP area has already been protected, R/B# goes LOW for tOBSY. After tOBSY, the status register is set to 60h. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 97 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP One-Time Programmable (OTP) Operations Figure 68: OTP DATA PROTECT Operation (After Entering OTP Protect Mode) CLE CE# tWC WE# tWB tPROG ALE RE# I/Ox Col 00h 80h OTP DATA PROTECT command Col 00h OTP page 00h 00h DIN OTP address 10h 70h PROGRAM command READ STATUS command R/B# Status OTP data protected1 Don’t Care Note: 1. OTP data is protected following a good status confirmation. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 98 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP One-Time Programmable (OTP) Operations OTP DATA READ (00h-30h) To read data from the OTP area, set the device to OTP operation mode, then issue the PAGE READ (00h-30h) command. Data can be read from OTP pages within the OTP area whether the area is protected or not. To use the PAGE READ command for reading data from the OTP area, issue the 00h command, and then issue five address cycles: for the first two cycles, the column address; and for the remaining address cycles, select a page in the range of 02h-00h-00h through 1Fh-00h-00h. Lastly, issue the 30h command. The PAGE READ CACHE MODE command is not supported on OTP pages. R/B# goes LOW (tR) while the data is moved from the OTP page to the data register. The READ STATUS (70h) command is the only valid command for reading status in OTP operation mode. Bit 5 of the status register reflects the state of R/B# (see Status Operations). Normal READ operation timings apply to OTP read accesses. Additional pages within the OTP area can be selected by repeating the OTP DATA READ command. The PAGE READ command is compatible with the RANDOM DATA OUTPUT (05h-E0h) command. Only data on the current page can be read. Pulsing RE# outputs data sequentially. Figure 69: OTP DATA READ CLE CE# WE# ALE tR RE# I/Ox 00h Col add 1 Col add 2 OTP page1 00h 00h OTP address DOUT n 30h DOUT n+1 DOUT m Busy R/B# Don’t Care Note: 1. The OTP page must be within the 02h–1Fh range. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 99 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP One-Time Programmable (OTP) Operations Figure 70: OTP DATA READ with RANDOM DATA READ Operation CLE tCLR CE# WE# tWB tAR tWHR ALE tREA tRC RE# tRR I/Ox 00h Col add 1 Col add 2 OTP page1 00h 00h DOUT n 30h DOUT n+1 05h tR Column addressn Col add 1 Col add 2 E0h DOUT m DOUT m+1 Column addressm Busy R/B# Don’t Care Note: 1. The OTP page must be within the range 02h–1Fh. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 100 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Two-Plane Operations Two-Plane Operations Each NAND Flash logical unit (LUN) is divided into multiple physical planes. Each plane contains a cache register and a data register independent of the other planes. The planes are addressed via the low-order block address bits. Specific details are provided in Device and Array Organization. Two-plane operations make better use of the NAND Flash arrays on these physical planes by performing concurrent READ, PROGRAM, or ERASE operations on multiple planes, significantly improving system performance. Two-plane operations must be of the same type across the planes; for example, it is not possible to perform a PROGRAM operation on one plane with an ERASE operation on another. When issuing two-plane program or erase operations, use the READ STATUS (70h) command and check whether the previous operation(s) failed. If the READ STATUS (70h) command indicates that an error occurred (FAIL = 1 and/or FAILC = 1), use the READ STATUS ENHANCED (78h) command to determine which plane operation failed. Two-Plane Addressing Two-plane commands require multiple, five-cycle addresses, one address per operational plane. For a given two-plane operation, these addresses are subject to the following requirements: • The LUN address bit(s) must be identical for all of the issued addresses. • The plane select bit, BA[6], must be different for each issued address. • The page address bits, PA[5:0], must be identical for each issued address. The READ STATUS (70h) command should be used following two-plane program page and erase block operations on a single die (LUN). PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 101 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Two-Plane Operations Figure 71: TWO-PLANE PAGE READ CLE WE# ALE RE# Page address M 00h I/Ox Col add 1 Col add 2 Row add 1 Column address J Row add 2 Page address M Row add 3 Col add 1 00h Col add 2 Row add 1 Column address J Plane 0 address Row add 2 Row add 3 30h tR Plane 1 address R/B# 1 CLE WE# ALE RE# I/Ox DOUT 0 DOUT 1 DOUT 06h Col add 1 Col add 2 Row add 1 Plane 0 data Row add 2 Row add 3 Plane 1 address E0h DOUT 0 DOUT 1 DOUT Plane 1 data R/B# 1 Notes: 1. Column and page addresses must be the same. 2. The least significant block address bit, BA6, must be different for the first- and secondplane addresses. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 102 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Two-Plane Operations Figure 72: TWO-PLANE PAGE READ with RANDOM DATA READ tR R/B# RE# I/Ox 00h Address (5 cycles) 00h Address (5 cycles) 30h Plane 0 address Data output Plane 1 address 05h Address (2 cycles) E0h Data output Plane 0 data Plane 0 data 1 R/B# RE# 06h I/Ox Address (5 cycles) E0h Data output 05h Address (2 cycles) E0h Data output Plane 1 data Plane 1 address Plane 1 data 1 Figure 73: TWO-PLANE PROGRAM PAGE tDBSY tPROG R/B# I/Ox 80h Address (5 cycles) Data 1st-plane address PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 input 11h 80h Address (5 cycles) Data input 10h 70h Status 2nd-plane address 103 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Two-Plane Operations Figure 74: TWO-PLANE PROGRAM PAGE with RANDOM DATA INPUT tDBSY R/B# I/Ox 80h Address (5 cycles) Data input 85h Address (2 cycles) Data input Different column address than previous 5 address cycles, for 1st plane only 1st-plane address 11h 80h Address (5 cycles) Data input 2nd-plane address 1 Unlimited number of repetitions tPROG R/B# 85h I/Ox 1 Address (2 cycles) Data input 10h Different column address than previous 5 address cycles, for 2nd plane only Unlimited number of repetitions PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 104 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Two-Plane Operations Figure 75: TWO-PLANE PROGRAM PAGE CACHE MODE tDBSY tCBSY R/B# 80h I/Ox Address/data input 80h 11h 1st plane Address/data input 15h 2nd plane 1 tDBSY tCBSY R/B# 80h I/Ox Address/data input 11h 80h 1st plane Address/data input 15h 2nd plane 1 2 tDBSY tLPROG R/B# 80h I/Ox Address/data input 11h 80h 1st plane Address/data input 10h 2nd plane 2 PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 105 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Two-Plane Operations Figure 76: TWO-PLANE INTERNAL DATA MOVE tR tDBSY R/B# 00h I/Ox Address (5 cycles) 00h 1st-plane source Address (5 cycles) 35h 85h 2nd-plane source Address (5 cycles) 11h 1st-plane destination 1 tPROG R/B# 85h I/Ox Address (5 cycles) 10h 70h Status 2nd-plane destination 1 PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 106 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Two-Plane Operations Figure 77: TWO-PLANE INTERNAL DATA MOVE with TWO-PLANE RANDOM DATA READ tR R/B# RE# I/Ox 00h Address (5 cycles) 00h Address (5 cycles) 35h 1st-plane source Data output 2nd-plane source 06h Data from 1st-plane source Address (5 cycles) E0h 2nd-plane source address 1 R/B# RE# Data output I/Ox 05h Data from 2nd-plane source 1 Data output Address (2 cycles) E0h 2nd-plane source column address Data from 2nd-plane source from new column address 2 Optional tDBSY tPROG R/B# RE# I/Ox 85h 2 Address (5 cycles) 11h 1st-plane destination PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 85h Address (5 cycles) 10h 70h Status 2nd-plane destination 107 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Two-Plane Operations Figure 78: TWO-PLANE INTERNAL DATA MOVE with RANDOM DATA INPUT tR R/B# 00h I/Ox Address (5 cycles) 00h Address (5 cycles) 1st-plane source 35h 85h 2nd-plane source Address (5 cycles) Data 85h Optional 1st-plane destination Address (2 cycles) Data 11h Unlimited number of repetitions 1 tPROG tDBSY R/B# 85h I/Ox Address (5 cycles) Data Optional 2nd-plane destination 85h Address (2 cycles) Data 10h 70h Status Unlimited number of repetitions 1 PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 108 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Two-Plane Operations Figure 79: TWO-PLANE BLOCK ERASE CLE CE# WE# ALE tDBSY tBERS R/B# RE# I/Ox 60h Address input (3 cycles) D1h 60h 1st plane Address input (3 cycles) D0h 70h Status or 78h 2nd plane Don‘t Care Optional Figure 80: TWO-PLANE/MULTIPLE-DIE READ STATUS Cycle CE# CLE WE# tAR ALE RE# tWHR I/Ox 78h PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 Address (3 cycles) 109 tREA Status output Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Interleaved Die (Multi-LUN) Operations Interleaved Die (Multi-LUN) Operations In devices that have more than one die (LUN) per target, it is possible to improve performance by interleaving operations between the die (LUNs). An interleaved die (multiLUN) operation is one that is issued to an idle die (LUN) (RDY = 1) while another die (LUN) is busy (RDY = 0). Interleaved die (multi-LUN) operations are prohibited following RESET (FFh), identification (90h, ECh, EDh), and configuration (EEh, EFh) operations until ARDY =1 for all of the die (LUNs) on the target. During an interleaved die (multi-LUN) operation, there are two methods to determine operation completion. The R/B# signal indicates when all of the die (LUNs) have finished their operations. R/B# remains LOW while any die (LUN) is busy. When R/B# goes HIGH, all of the die (LUNs) are idle and the operations are complete. Alternatively, the READ STATUS ENHANCED (78h) command can report the status of each die (LUN) individually. If a die (LUN) is performing a cache operation, like PROGRAM PAGE CACHE (80h-15h), then the die (LUN) is able to accept the data for another cache operation when status register bit 6 is 1. All operations, including cache operations, are complete on a die when status register bit 5 is 1. During and following interleaved die (multi-LUN) operations, the READ STATUS (70h) command is prohibited. Instead, use the READ STATUS ENHANCED (78h) command to monitor status. This command selects which die (LUN) will report status. When twoplane commands are used with interleaved die (multi-LUN) operations, the two-plane commands must also meet the requirements in Two-Plane Operations. See Command Definitions for the list of commands that can be issued while other die (LUNs) are busy. During an interleaved die (multi-LUN) operation that involves a PROGRAM series (80h-10h, 80h-15h) operation and a READ operation, the PROGRAM series operation must be issued before the READ series operation. The data from the READ series operation must be output to the host before the next PROGRAM series operation is issued. This is because the 80h command clears the cache register contents of all cache registers on all planes. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 110 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Error Management Error Management Each NAND Flash die (LUN) is specified to have a minimum number of valid blocks (NVB) of the total available blocks. This means the die (LUNs) could have blocks that are invalid when shipped from the factory. An invalid block is one that contains at least one page that has more bad bits than can be corrected by the minimum required ECC. Additional blocks can develop with use. However, the total number of available blocks per die (LUN) will not fall below NVB during the endurance life of the product. Although NAND Flash memory devices could contain bad blocks, they can be used quite reliably in systems that provide bad block management and error-correction algorithms. This type of software environment ensures data integrity. Internal circuitry isolates each block from other blocks, so the presence of a bad block does not affect the operation of the rest of the NAND Flash array. NAND Flash devices are shipped from the factory erased. The factory identifies invalid blocks before shipping by attempting to program the bad block mark into every location in the first page of each invalid block. It may not be possible to program every location with the bad block mark. However, the first spare area location in each bad block is guaranteed to contain the bad block mark. This method is compliant with ONFI Factory Defect Mapping requirements. See the following table for the first spare area location and the bad block mark. System software should check the first spare area location on the first page of each block prior to performing any PROGRAM or ERASE operations on the NAND Flash device. A bad block table can then be created, enabling system software to map around these areas. Factory testing is performed under worst-case conditions. Because invalid blocks could be marginal, it may not be possible to recover this information if the block is erased. Over time, some memory locations may fail to program or erase properly. In order to ensure that data is stored properly over the life of the NAND Flash device, the following precautions are required: • Always check status after a PROGRAM or ERASE operation • Under typical conditions, use the minimum required ECC (see table below) • Use bad block management and wear-leveling algorithms The first block (physical block address 00h) for each CE# is guaranteed to be valid with ECC when shipped from the factory. Table 24: Error Management Details Description Requirement Minimum number of valid blocks (NVB) per LUN 4016 Total available blocks per LUN 4096 First spare area location x8: byte 2048 x16: word 1024 Bad-block mark x8: 00h x16: 0000h Minimum required ECC 4-bit ECC per 528 bytes PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 111 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Error Management Table 24: Error Management Details (Continued) Description Requirement Minimum ECC with internal ECC enabled 4-bit ECC per 516 bytes (user data) + 8 bytes (parity data) Minimum required ECC for block 0 if PROGRAM/ ERASE cycles are less than 1000 1-bit ECC per 528 bytes PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 112 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Internal ECC and Spare Area Mapping for ECC Internal ECC and Spare Area Mapping for ECC Internal ECC enables 5-bit detection and 4-bit error correction in 512 bytes (x8) or 256 words (x16) of the main area and 4 bytes (x8) or 2 words (x16) of metadata I in the spare area. The metadata II area, which consists of two bytes (x8) and one word (x16), is not ECC protected. During the busy time for PROGRAM operations, internal ECC generates parity bits when error detection is complete. During READ operations the device executes the internal ECC engine (5-bit detection and 4-bit error correction). When the READ operaton is complete, read status bit 0 must be checked to determine whether errors larger than four bits have occurred. Following the READ STATUS command, the device must be returned to read mode by issuing the 00h command. Limitations of internal ECC include the spare area, defined in the figures below, and ECC parity areas that cannot be written to. Each ECC user area (referred to as main and spare) must be written within one partial-page program so that the NAND device can calculate the proper ECC parity. The number of partial-page programs within a page cannot exceed four. Figure 81: Spare Area Mapping (x8) Max Byte Min Byte Address Address ECC Protected 1FFh 000h Yes 3FFh 200h Yes 5FFh 400h Yes 7FFh 600h Yes 801h 800h No 803h 802h No 807h 804h Yes 80Fh 808h Yes 811h 810h No 813h 812h No 817h 814h Yes 81Fh 818h Yes 821h 820h No 823h 822h No 827h 824h Yes 82Fh 828h Yes 831h 830h No 833h 832h No 837h 834h Yes 83Fh 838h Yes PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 Area Main 0 Main 1 Main 2 Main 3 Spare 0 Spare 0 Spare 1 Spare 1 Spare 2 Spare 2 Spare 3 Spare 3 Description User data User data User data User data Reserved User metadata II User metadata I ECC for main/spare 0 Reserved User metadata II User metadata I ECC for main/spare 1 Reserved User metadata II User metadata I ECC for main/spare 2 User data User metadata II User metadata I ECC for main/spare 3 113 Bad Block Information ECC Parity User Data (Metadata) 2 bytes 8 bytes 6 bytes Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Internal ECC and Spare Area Mapping for ECC Figure 82: Spare Area Mapping (x16) Max word Min word Address Address ECC Protected 0FFh 000h Yes 1FFh 100h Yes 2FFh 200h Yes 3FFh 300h Yes 400h 400h No 401h 401h No 403h 402h Yes 407h 404h Yes 408h 408h No 409h 409h No 40Bh 40Ah Yes 40Fh 40Ch Yes 410h 410h No 411h 411h No 413h 412h Yes 417h 414h Yes 418h 418h No 419h 419h No 41Bh 41Ah Yes 41Fh 41Ch Yes PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 Area Main 0 Main 1 Main 2 Main 3 Spare 0 Spare 0 Spare 1 Spare 1 Spare 2 Spare 2 Spare 3 Spare 3 Description User data User data User data User data Reserved User metadata II User metadata I ECC for main/spare 0 Reserved User metadata II User metadata I ECC for main/spare 1 Reserved User metadata II User metadata I ECC for main/spare 2 User data User metadata II User metadata I ECC for main/spare 3 114 Bad Block Information ECC Parity User Data (Metadata) 1 word 4 words 3 words Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Electrical Specifications Electrical Specifications Stresses greater than those listed can cause permanent damage to the device. This is stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not guaranteed. Exposure to absolute maximum rating conditions for extended periods can affect reliability. Table 25: Absolute Maximum Ratings Voltage on any pin relative to Vss Parameter/Condition Voltage input Symbol Min Max Unit VIN –0.6 2.4 V –0.6 4.6 V –0.6 2.4 V –0.6 4.6 V TSTG –65 150 °C – – 5 mA 1.8V 3.3V VCC supply voltage 1.8V VCC 3.3V Storage temperature Short circuit output current, I/Os Table 26: Recommended Operating Conditions Parameter/Condition Symbol Min Typ Max Unit TA 0 – 70 °C Operating temperature Commercial Industrial VCC supply voltage 1.8V VCC 3.3V Ground supply voltage VSS –40 – 85 °C 1.7 1.8 1.95 V 2.7 3.3 3.6 V 0 0 0 V Table 27: Valid Blocks Notes: Parameter Symbol Device Min Max Unit Notes Valid block number NVB MT29F4G 4016 4096 Blocks 1, 2 MT29F8G 8032 8192 Blocks 1, 2, 3 1. Invalid blocks are blocks that contain one or more bad bits. The device may contain bad blocks upon shipment. Additional bad blocks may develop over time; however, the total number of available blocks will not drop below NVB during the endurance life of the device. Do not erase or program blocks marked invalid by the factory. 2. Block 00h (the first block) is guaranteed to be valid with ECC when shipped from the factory. 3. Each 4Gb section has a maximum of 80 invalid blocks. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 115 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Electrical Specifications Table 28: Capacitance Notes 1–3 apply to all parameters and conditions Description Symbol Notes: Max Unit Input capacitance CIN 10 pF Input/output capacitance (I/O) CIO 10 pF 1. These parameters are verified in device characterization and are not 100% tested. 2. Test conditions: TC = 25°C; f = 1 MHz; VIN = 0V. 3. Capacitance (CIN = CIO = 20pF) for MT29F8G and (CIN = CIO = 40pF) for MT29F16G. Table 29: Test Conditions Parameter Value Input pulse levels Notes 0.0V to VCC Input rise and fall times 1.8V 2.5ns 3.3V 5.0ns VCC/2 Input and output timing levels Output load 1 TTL GATE and CL = 30pF (1.8V) 1 1 TTL GATE and CL = 50pF (3.3V) Output load 1 TTL GATE and CL = 30pF (1.8V) 1 1 TTL GATE and CL = 50pF (3.3V) Note: 1. Verified in device characterization, not 100% tested. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 116 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Electrical Specifications – DC Characteristics and Operating Conditions Electrical Specifications – DC Characteristics and Operating Conditions Table 30: DC Characteristics and Operating Conditions (3.3V) Parameter Conditions Sequential READ current tRC = tRC (MIN); CE# = VIL; IOUT = 0mA Symbol Min Typ Max Unit ICC1 – 25 35 mA Notes PROGRAM current – ICC2 – 25 35 mA ERASE current – ICC3 – 25 35 mA CE# = VIH; WP# = 0V/VCC ISB1 – – 1 mA Standby current (CMOS) CE# = VCC - 0.2V; WP# = 0V/VCC ISB2 – 20 100 μA Staggered power-up current Rise time = 1ms Line capacitance = 0.1μF IST – – 10 per die mA VIN = 0V to VCC ILI – – ±10 μA VOUT = 0V to VCC ILO – – ±10 μA I/O[7:0], I/O[15:0], CE#, CLE, ALE, WE#, RE#, WP# VIH 0.8 x VCC – VCC + 0.3 V – VIL –0.3 – 0.2 x VCC V Output high voltage IOH = –400μA VOH 0.67 x VCC – – V 3 Output low voltage IOL = 2.1mA VOL – – 0.4 V 3 Output low current VOL = 0.4V IOL (R/B#) 8 10 – mA 2 Standby current (TTL) Input leakage current Output leakage current Input high voltage Input low voltage, all inputs Notes: 1 1. Measurement is taken with 1ms averaging intervals and begins after VCC reaches VCC(MIN). 2. IOL (R/B#) may need to be relaxed if R/B pull-down strength is not set to full. 3. VOH and VOL may need to be relaxed if I/O drive strength is not set to full. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 117 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Electrical Specifications – DC Characteristics and Operating Conditions Table 31: DC Characteristics and Operating Conditions (1.8V) Parameter Conditions Sequential READ current tRC = tRC (MIN); CE# = VIL; IOUT = 0mA Symbol Min Typ Max Unit Notes ICC1 – 13 20 mA 1, 2 PROGRAM current – ICC2 – 10 20 mA 1, 2 ERASE current – ICC3 – 10 20 mA 1, 2 CE# = VIH; WP# = 0V/VCC ISB1 – – 1 mA Standby current (CMOS) CE# = VCC - 0.2V; WP# = 0V/VCC ISB2 – 10 50 μA Staggered power-up current Rise time = 1ms Line capacitance = 0.1μF IST – – 10 per die mA VIN = 0V to VCC ILI – – ±10 μA VOUT = 0V to VCC ILO – – ±10 μA I/O[7:0], I/O[15:0], CE#, CLE, ALE, WE#, RE#, WP# VIH 0.8 x VCC – VCC + 0.3 V – VIL –0.3 – 0.2 x VCC V Output high voltage IOH = –100μA VOH VCC - 0.1 – – V 4 Output low voltage IOL = +100μA VOL – – 0.1 V 4 VOL = 0.2V IOL (R/B#) 3 4 – mA 5 Standby current (TTL) Input leakage current Output leakage current Input high voltage Input low voltage, all inputs Output low current (R/B#) Notes: 3 1. Typical and maximum values are for single-plane operation only. If device supports dualplane operation, values are 20mA (TYP) and 40mA (MAX). 2. Values are for single-die operations. Values could be higher for interleaved-die operations. 3. Measurement is taken with 1ms averaging intervals and begins after VCC reaches VCC(MIN). 4. Test conditions for VOH and VOL. 5. DC characteristics may need to be relaxed if R/B# pull-down strength is not set to full. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 118 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Electrical Specifications – AC Characteristics and Operating Conditions Electrical Specifications – AC Characteristics and Operating Conditions Table 32: AC Characteristics: Command, Data, and Address Input (3.3V) Note 1 applies to all Parameter Symbol Min Max Unit Notes ALE to data start tADL 70 – ns 2 ALE hold time tALH 5 – ns ALE setup time tALS 10 – ns CE# hold time tCH 5 – ns CLE hold time tCLH 5 – ns CLE setup time tCLS 10 – ns CE# setup time tCS 15 – ns Data hold time tDH 5 – ns Data setup time tDS 7 – ns WRITE cycle time tWC 20 – ns 2 WE# pulse width HIGH tWH 7 – ns 2 WE# pulse width tWP 10 – ns 2 WP# transition to WE# LOW tWW 100 – ns Notes: 1. Operating mode timings meet ONFI timing mode 5 parameters. 2. Timing for tADL begins in the address cycle, on the final rising edge of WE#, and ends with the first rising edge of WE# for data input. Table 33: AC Characteristics: Command, Data, and Address Input (1.8V) Note 1 applies to all Parameter Symbol Min Max Unit Notes ALE to data start tADL 70 – ns 2 ALE hold time tALH 5 – ns ALE setup time tALS 10 – ns CE# hold time tCH 5 – ns CLE hold time tCLH 5 – ns CLE setup time tCLS 10 – ns CE# setup time tCS 20 – ns Data hold time tDH 5 – ns Data setup time tDS 10 – ns WRITE cycle time tWC 25 – ns 2 WE# pulse width HIGH tWH 10 – ns 2 WE# pulse width tWP 12 – ns 2 WP# transition to WE# LOW tWW 100 – ns Notes: 1. Operating mode timings meet ONFI timing mode 4 parameters. 2. Timing for tADL begins in the address cycle on the final rising edge of WE#, and ends with the first rising edge of WE# for data input. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 119 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Electrical Specifications – AC Characteristics and Operating Conditions Table 34: AC Characteristics: Normal Operation (3.3V) Note 1 applies to all Parameter Symbol Min tAR 10 – ns CE# access time tCEA – 25 ns CE# HIGH to output High-Z tCHZ – 50 ns CLE to RE# delay tCLR 10 – ns CE# HIGH to output hold tCOH 15 – ns Output High-Z to RE# LOW tIR 0 – ns READ cycle time tRC 20 – ns RE# access time tREA – 16 ns RE# HIGH hold time tREH 7 – ns tRHOH 15 – ns RE# HIGH to WE# LOW tRHW 100 – ns RE# HIGH to output High-Z tRHZ – 100 ns ALE to RE# delay RE# HIGH to output hold Max Unit tRLOH 5 – ns RE# pulse width tRP 10 – ns Ready to RE# LOW tRR 20 – ns Reset time (READ/PROGRAM/ERASE) tRST – 5/10/500 μs WE# HIGH to busy tWB – 100 ns tWHR 60 – ns RE# LOW to output hold WE# HIGH to RE# LOW Notes: Notes 2 2 3 1. AC characteristics may need to be relaxed if I/O drive strength is not set to full. 2. Transition is measured ±200mV from steady-state voltage with load. This parameter is sampled and not 100% tested. 3. The first time the RESET (FFh) command is issued while the device is idle, the device will go busy for a maximum of 1ms. Thereafter, the device goes busy for a maximum of 5μs. Table 35: AC Characteristics: Normal Operation (1.8V) Note 1 applies to all Parameter Symbol Min tAR 10 – ns CE# access time tCEA – 25 ns CE# HIGH to output High-Z tCHZ – 50 ns CLE to RE# delay tCLR 10 – ns CE# HIGH to output hold tCOH 15 – ns Output High-Z to RE# LOW tIR 0 – ns READ cycle time tRC 25 – ns RE# access time tREA – 22 ns RE# HIGH hold time tREH 10 – ns tRHOH 15 – ns tRHW 100 – ns ALE to RE# delay RE# HIGH to output hold RE# HIGH to WE# LOW PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 120 Max Unit Notes 2 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Electrical Specifications – AC Characteristics and Operating Conditions Table 35: AC Characteristics: Normal Operation (1.8V) (Continued) Note 1 applies to all Parameter RE# HIGH to output High-Z RE# LOW to output hold Symbol Min Max Unit Notes tRHZ – 65 ns 2 tRLOH 3 – ns RE# pulse width tRP 12 – ns Ready to RE# LOW tRR 20 – ns Reset time (READ/PROGRAM/ERASE) tRST – 5/10/500 μs WE# HIGH to busy tWB – 100 ns tWHR 80 – ns WE# HIGH to RE# LOW Notes: 3 1. AC characteristics may need to be relaxed if I/O drive strength is not set to full. 2. Transition is measured ±200mV from steady-state voltage with load. This parameter is sampled and not 100% tested. 3. The first time the RESET (FFh) command is issued while the device is idle, the device will be busy for a maximum of 1ms. Thereafter, the device is busy for a maximum of 5μs. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 121 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Electrical Specifications – Program/Erase Characteristics Electrical Specifications – Program/Erase Characteristics Table 36: Program/Erase Characteristics Parameter Number of partial-page programs Symbol Typ Max Unit Notes 4 cycles 1 NOP – BLOCK ERASE operation time tBERS 0.7 3 ms Busy time for PROGRAM CACHE operation tCBSY 3 600 μs tRCBSY 3 25 μs Busy time for SET FEATURES and GET FEATURES operations tFEAT – 1 μs Busy time for OTP DATA PROGRAM operation if OTP is protected tOBSY – 30 μs Busy time for PROGRAM/ERASE on locked blocks tLBSY – 3 μs PROGRAM PAGE operation time, internal ECC disabled tPROG 200 600 μs 8 PROGRAM PAGE operation time, internal ECC enabled tPROG_ECC 220 600 μs 3, 8 Data transfer from Flash array to data register, internal ECC disabled tR – 25 μs 6, 7 Data transfer from Flash array to data register, internal ECC enabled tR_ECC 45 70 μs 3, 5 Busy time for OTP DATA PROGRAM operation if OTP is protected, internal ECC enabled tOBSY_ECC – 50 μs Busy time for TWO-PLANE PROGRAM PAGE or TWO-PLANE BLOCK ERASE operation tDBSY 0.5 1 μs Cache read busy time Notes: 2 1. Four total partial-page programs to the same page. If ECC is enabled, then the device is limited to one partial-page program per ECC user area, not exceeding four partial-page programs per page. 2. tCBSY MAX time depends on timing between internal program completion and data-in. 3. Parameters are with internal ECC enabled. 4. Typical is nominal voltage and room temperature. 5. Typical tR_ECC is under typical process corner, nominal voltage, and at room temperature. 6. Data transfer from Flash array to data register with internal ECC disabled. 7. AC characteristics may need to be relaxed if I/O drive strength is not set to full. 8. Typical program time is defined as the time within which more than 50% of the pages are programmed at nominal voltage and room temperature. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 122 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Asynchronous Interface Timing Diagrams Asynchronous Interface Timing Diagrams Figure 83: RESET Operation CLE CE# tWB WE# tRST R/B# I/O[7:0] FFh RESET command Figure 84: READ STATUS Cycle tCLR CLE CE# tCLS tCLH tCS tWP tCH WE# tCEA tWHR tRP tCHZ tCOH RE# tRHZ tDS I/O[7:0] tDH tIR tREA tRHOH Status output 70h Don’t Care PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 123 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Asynchronous Interface Timing Diagrams Figure 85: READ STATUS ENHANCED Cycle tCS CE# tCLS tCLH CLE tWC tWP tWP tWH tCH WE# tCHZ tCEA tALS tALH tALH tCOH tAR ALE RE# tRHZ tDS I/O[7:0] tDH tWHR Row add 1 78h Row add 2 tREA tRHOH Status output Row add 3 Don’t Care Figure 86: READ PARAMETER PAGE CLE WE# tWB ALE tRC RE# tRR I/O[7:0] ECh 00h tR or tR_ECC tRP P00 P10 P2550 P01 R/B# PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 124 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Asynchronous Interface Timing Diagrams Figure 87: READ PAGE CLE tCLR CE# tWC WE# tWB tAR ALE tR tRC or tR_ECC tRHZ RE# tRR I/Ox 00h Col add 1 Col add 2 Row add 1 Row add 2 Row add 3 tRP DOUT N 30h DOUT N+1 DOUT M Busy RDY Don’t Care PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 125 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Asynchronous Interface Timing Diagrams Figure 88: READ PAGE Operation with CE# “Don’t Care” CLE CE# RE# ALE tR or tR_ECC RDY WE# I/Ox 00h Address (5 cycles) 30h Data output tCEA CE# tREA tCOH RE# Don’t Care Out I/Ox PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 tCHZ 126 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Asynchronous Interface Timing Diagrams Figure 89: RANDOM DATA READ CLE tCLR CE# WE# tRHW tWHR ALE tRC tREA RE# I/Ox DOUT N-1 DOUT N 05h Col add 1 Col add 2 E0h DOUT M DOUT M+1 Column address M RDY PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 127 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Asynchronous Interface Timing Diagrams Figure 90: READ PAGE CACHE SEQUENTIAL CLE tCLS tCLS tCLH tCLH tCS tCH tCS tCH CE# tWC WE# tCEA tRHW ALE tRC RE# tWB tDH tDS tR tWB I/Ox Col add 1 00h Col add 2 Row add 1 Column address 00h Row add 2 Row add 3 tREA tDS tRR 30h Dout 0 31h Page address M Dout 1 Dout tDH 31h Page address M tRCBSY RDY Column address 0 1 CLE tCLS tCLH tCS tCH CE# WE# tRHW tRHW tCEA ALE tRC tRC RE# tWB tREA tDS tRR tDH I/Ox Dout 0 Dout 1 Dout 31h Page address M tREA Dout 0 tRCBSY Dout 1 Dout Page address M+1 Dout 0 3Fh tRCBSY Dout 1 Dout Page address M+2 RDY Column address 0 Column address 0 Column address 0 1 PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 Don’t Care 128 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Asynchronous Interface Timing Diagrams Figure 91: READ PAGE CACHE RANDOM CLE tCLS tCLH tCH tCS CE# tWC WE# ALE RE# tDH tWB tDS I/Ox Col add 1 00h Row add 1 Col add 2 Column address 00h Row add 2 Row add 3 tR 30h Col add 1 00h Page address M Row add 1 Col add 2 Column address 00h Row add 2 Page address N RDY 1 CLE tCLS tCLH tCS tCH CE# WE# tCEA tRHW ALE tRC tWB RE# tDS tDH I/Ox Col add 1 Row add 1 Col add 2 Column address 00h Row add 2 Row add 3 Page address N RDY tRR tREA Dout 0 31h Dout 1 Page address M tRCBSY Column address 0 1 PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 Dout Dout 0 3Fh tRCBSY Dout 1 Dout Page address N Column address 0 Don’t Care 129 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Asynchronous Interface Timing Diagrams Figure 92: READ ID Operation CLE CE# WE# tAR ALE RE# tWHR I/Ox 90h tREA Byte 1 Byte 0 00h or 20h Byte 2 Byte 3 Byte 4 Address, 1 cycle Figure 93: PROGRAM PAGE Operation CLE CE# tWC tADL WE# tWB tPROG or tWHR tPROG_ECC ALE RE# I/Ox 80h Col add 1 Col add 2 Row add 1 Row add 2 Row add 3 DIN N DIN M 10h 70h Status 1 up to m byte serial Input RDY Don’t Care PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 130 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Asynchronous Interface Timing Diagrams Figure 94: PROGRAM PAGE Operation with CE# “Don’t Care” CLE CE# WE# ALE I/Ox 80h Address (5 cycles) Data input Data input 10h tCH tCS CE# tWP WE# Don’t Care Figure 95: PROGRAM PAGE Operation with RANDOM DATA INPUT CLE CE# tWC tADL tADL WE# tPROG or tWB tPROG_ECC tWHR ALE RE# I/Ox 80h Col add 1 Col add 2 Row add 1 Row add 2 Row add 3 DIN M DIN N Serial input 85h Col add 1 Col add 2 CHANGE WRITE Column address COLUMN command DIN P DIN Q Serial input 10h 70h Status READ STATUS command RDY Don’t Care PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 131 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Asynchronous Interface Timing Diagrams Figure 96: PROGRAM PAGE CACHE CLE CE# tADL tWC WE# tWB tCBSY tWB tLPROG tWHR ALE RE# I/Ox 80h Row Row Row Col Col add 1 add 2 add 1 add 2 add 3 Din N Din M 15h 80h Col Col Row Row Row add 1 add 2 add 1 add 2 add 3 Din N Din M 10h 70h Status Serial input RDY Last page - 1 Last page Don’t Care Figure 97: PROGRAM PAGE CACHE Ending on 15h CLE CE# tWC tADL tADL WE# tWHR tWHR ALE RE# I/Ox 80h Col Row Row Row Col add 1 add 2 add 1 add 2 add 3 Din Din N M Serial input 15h 70h Status 80h Col Row Row Row Din Col add 1 add 2 add 1 add 2 add 3 N Last page – 1 Din M 15h 70h Status 70h Status Last page Poll status until: I/O6 = 1, Ready To verify successful completion of the last 2 pages: I/O5 = 1, Ready I/O0 = 0, Last page PROGRAM successful I/O1 = 0, Last page – 1 PROGRAM successful Don’t Care PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 132 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Asynchronous Interface Timing Diagrams Figure 98: INTERNAL DATA MOVE CLE CE# tADL tWC WE# tWB tPROG tWB tWHR ALE RE# I/Ox tR Col add 1 00h Col add 2 Row add 1 Row add 2 Row add 3 35h (or 30h) 85h Col Row Row Row Col add 1 add 2 add 1 add 2 add 3 Data 1 Data N 10h Status 70h READ STATUS Busy command Busy RDY Data Input Optional Don’t Care Figure 99: INTERNAL DATA MOVE (85h-10h) with Internal ECC Enabled tR_ECC tPROG_ECC R/B# I/O[7:0] 00h Address (5 cycles) 35h Source address PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 70h Status 00h SR bit 0 = 0 READ successful SR bit 1 = 0 READ error DOUT 85h DOUT is optional 133 Address (5 cycles) 10h Destination address 70h Status 00h SR bit 0 = 0 READ successful SR bit 1 = 0 READ error Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Asynchronous Interface Timing Diagrams Figure 100: INTERNAL DATA MOVE (85h-10h) with Random Data Input with Internal ECC Enabled tR_ECC tPROG_ECC R/B# I/O[7:0] 00h Address (5 cycles) 35h 70h Source address Status DOUT 00h SR bit 0 = 0 READ successful SR bit 1 = 0 READ error 85h DOUT is optional Address (5 cycles) Data 85h Address (2 cycles) Data 10h 70h Destination address Column address 1, 2 (Unlimitted repetitions are possible) Figure 101: ERASE BLOCK Operation CLE CE# t WC WE# t t WB WHR ALE RE# t I/O[7:0] 60h Row add 1 Row add 2 Row add 3 BERS D0h 70h Row address RDY Status READ STATUS command Busy I/O0 = 0, Pass I/O0 = 1, Fail PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 134 Don’t Care Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP 2Gb: x16, x32 Mobile LPDDR SDRAM 2Gb: x16, x32 Mobile LPDDR SDRAM Features • VDD/VDDQ = 1.70–1.95V • Bidirectional data strobe per byte of data (DQS) • Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle • Differential clock inputs (CK and CK#) • Commands entered on each positive CK edge • DQS edge-aligned with data for READs; center-aligned with data for WRITEs • 4 internal banks for concurrent operation • Data masks (DM) for masking write data; one mask per byte • Programmable burst lengths (BL): 2, 4, 8, or 16 • Concurrent auto precharge option is supported • Auto refresh and self refresh modes • 1.8V LVCMOS-compatible inputs • Temperature-compensated self refresh (TCSR) • Partial-array self refresh (PASR) • Deep power-down (DPD) • Status read register (SRR) • Selectable output drive strength (DS) • Clock stop capability • 64ms refresh; 32ms for the automotive temperature range PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 135 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP 2Gb: x16, x32 Mobile LPDDR SDRAM Table 37: Configuration Addressing – 2Gb Architecture 128 Meg x 16 64 Meg x 32 Configuration 32 Meg x 16 x 4 banks 16 Meg x 32 x 4 banks Refresh count Row addressing Column addressing Reduced Page-Size Option 128 Meg x 16 Reduced Page-Size Option 64 Meg x 32 32 Meg x 16 x 4 banks 16 Meg x 32 x 4 banks 8K 8K 8K 8K 16K A[13:0] 16K A[13:0] 32K A[14:0] 32K A[14:0] 2K A11, A[9:0] 1K A[9:0] 1K A[9:0] 512K A[8:0] PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 136 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP 2Gb: x16, x32 Mobile LPDDR SDRAM General Description The 2Gb Mobile low-power DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 2,147,483,648 bits. It is internally configured as a quad-bank DRAM. Each of the x16’s 536,870,912-bit banks is organized as 16,384 rows by 2048 columns by 16 bits. Each of the x32’s 536,870,912-bit banks is organized as 16,384 rows by 1024 columns by 32 bits. In the reduced page-size (LG) option, each of the x32's 536,870,912-bit banks is organized as 32,768 rows by 512 columns by 32 bits. In the reduced page-size (R4) option, each of the x16's 536,870,912-bit banks is organized as 32,768 rows by 1024 columns x 16 bits. Note: 1. Throughout this data sheet, various figures and text refer to DQs as “DQ.” DQ should be interpreted as any and all DQ collectively, unless specifically stated otherwise. Additionally, the x16 is divided into 2 bytes: the lower byte and the upper byte. For the lower byte (DQ[7:0]), DM refers to LDM and DQS refers to LDQS. For the upper byte (DQ[15:8]), DM refers to UDM and DQS refers to UDQS. The x32 is divided into 4 bytes. For DQ[7:0], DM refers to DM0 and DQS refers to DQS0. For DQ[15:8], DM refers to DM1 and DQS refers to DQS1. For DQ[23:16], DM refers to DM2 and DQS refers to DQS2. For DQ[31:24], DM refers to DM3 and DQS refers to DQS3. 2. Complete functionality is described throughout the document; any page or diagram may have been simplified to convey a topic and may not be inclusive of all requirements. 3. Any specific requirement takes precedence over a general statement. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 137 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Functional Block Diagrams Functional Block Diagrams Figure 102: Functional Block Diagram (x16) CKE CK# CK WE# CAS# RAS# Command decode CS# Control logic Bank 3 Bank 2 Bank 1 Refresh counter Standard mode register Extended mode register Bank 0 rowaddress latch and decoder Rowaddress Mux Bank 0 memory array Data 16 32 Read latch Sense amplifiers 16 MUX DRVRS 16 2 DQS generator DQ[15:0] COL 0 I/O gating DM mask logic 2 Address BA0, BA1 Address register 2 CK 32 Bank control logic 2 DQS Input registers 32 Column decoder Columnaddress counter/ latch Write FIFO and drivers CK out CK in LDQS, UDQS 2 Mask 2 2 2 16 16 16 16 4 32 RCVRS 16 LDM, UDM Data CK 2 COL 0 1 PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 138 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Functional Block Diagrams Figure 103: Functional Block Diagram (x32) CKE CK# CK WE# CAS# RAS# Command decode CS# Control logic Bank 3 Bank 2 Bank 1 Refresh counter Standard mode register Extended mode register Bank 0 rowaddress latch and decoder Rowaddress MUX Bank 0 memory array Data 32 64 Read latch Sense amplifiers 32 MUX DRVRS 32 2 DQS generator DQ[31:0] COL 0 I/O gating DM mask logic 2 Address, BA0, BA1 Address register 2 CK 64 Bank control logic DQS Input registers 4 4 4 4 32 32 Mask 64 Column decoder Columnaddress counter/ latch Write FIFO and drivers CK out CK in DQS0 DQS1 DQS2 DQS3 4 8 64 RCVRS 32 32 32 Data CK DM0 DM1 DM2 DM3 4 COL 0 1 PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 139 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Electrical Specifications Electrical Specifications Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Table 38: Absolute Maximum Ratings Note 1 applies to all parameters in this table Parameter Symbol Min Max Unit VDD/VDDQ supply voltage relative to VSS VDD/VDDQ –1.0 2.4 V Voltage on any pin relative to VSS VIN –0.5 2.4 or (VDDQ + 0.3V), whichever is less V Storage temperature (plastic) TSTG –55 150 ˚C Note: 1. VDD and VDDQ must be within 300mV of each other at all times. VDDQ must not exceed VDD. Table 39: AC/DC Electrical Characteristics and Operating Conditions Notes 1–5 apply to all parameters/conditions in this table; VDD/VDDQ = 1.70–1.95V Parameter/Condition Symbol Min Max Unit Notes Supply voltage VDD 1.70 1.95 V 6, 7 I/O supply voltage VDDQ 1.70 1.95 V 6, 7 Input voltage high VIH 0.8 × VDDQ VDDQ + 0.3 V 8, 9 Input voltage low VIL –0.3 0.2 × VDDQ V 8, 9 VIN –0.3 VDDQ + 0.3 V 10 DC input differential voltage VID(DC) 0.4 × VDDQ VDDQ + 0.6 V 10, 11 AC input differential voltage VID(AC) 0.6 × VDDQ VDDQ + 0.6 V 10, 11 VIX 0.4 × VDDQ 0.6 × VDDQ V 10, 12 DC input high voltage VIH(DC) 0.7 × VDDQ VDDQ + 0.3 V 8, 9, 13 DC input low voltage VIL(DC) –0.3 0.3 × VDDQ V 8, 9, 13 AC input high voltage VIH(AC) 0.8 × VDDQ VDDQ + 0.3 V 8, 9, 13 AC input low voltage VIL(AC) –0.3 0.2 × VDDQ V 8, 9, 13 DC output high voltage: Logic 1 (IOH = –0.1mA) VOH 0.9 × VDDQ – V DC output low voltage: Logic 0 (IOL = 0.1mA) VOL – 0.1 × VDDQ V II –1 1 μA Address and command inputs Clock inputs (CK, CK#) DC input voltage AC differential crossing voltage Data inputs Data outputs Leakage current Input leakage current Any input 0V ≤ VIN ≤ VDD (All other pins not under test = 0V) PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 140 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Electrical Specifications Table 39: AC/DC Electrical Characteristics and Operating Conditions (Continued) Notes 1–5 apply to all parameters/conditions in this table; VDD/VDDQ = 1.70–1.95V Parameter/Condition Symbol Min Output leakage current (DQ are disabled; 0V ≤ VOUT ≤ VDDQ) IOZ Max Unit –1.5 1.5 μA Notes Operating temperature Commercial TA 0 70 ˚C Wireless TA –25 85 ˚C Industrial TA –40 85 ˚C Automotive TA –40 105 ˚C Notes: 1. All voltages referenced to VSS. 2. All parameters assume proper device initialization. 3. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 4. Outputs measured with equivalent load; transmission line delay is assumed to be very small: 50 50 I/O I/O 10pF 20pF Full drive strength Half drive strength 5. Timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VDDQ/2 (or to the crossing point for CK/CK#). The output timing reference voltage level is VDDQ/2. 6. Any positive glitch must be less than one-third of the clock cycle and not more than +200mV or 2.0V, whichever is less. Any negative glitch must be less than one-third of the clock cycle and not exceed either –150mV or +1.6V, whichever is more positive. 7. VDD and VDDQ must track each other and VDDQ must be less than or equal to VDD. 8. To maintain a valid level, the transitioning edge of the input must: 8a. Sustain a constant slew rate from the current AC level through to the target AC level, VIL(AC) Or VIH(AC). 8b. Reach at least the target AC level. 8c. After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC). 9. VIH overshoot: VIHmax = VDDQ + 1.0V for a pulse width ≤3ns and the pulse width cannot be greater than one-third of the cycle rate. VIL undershoot: VILmin = –1.0V for a pulse width ≤3ns and the pulse width cannot be greater than one-third of the cycle rate. 10. CK and CK# input slew rate must be ≥1 V/ns (2 V/ns if measured differentially). 11. VID is the magnitude of the difference between the input level on CK and the input level on CK#. 12. The value of VIX is expected to equal VDDQ/2 of the transmitting device and must track variations in the DC level of the same. 13. DQ and DM input slew rates must not deviate from DQS by more than 10%. 50ps must be added to tDS and tDH for each 100 mV/ns reduction in slew rate. If slew rate exceeds 4 V/ns, functionality is uncertain. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 141 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Electrical Specifications Table 40: Capacitance (x16, x32) Notes 1 and 2 apply to all the parameters in this table Parameter Symbol Min Max Unit Input capacitance: CK, CK# CCK 1.0 2.0 pF Delta input capacitance: CK, CK# CDCK 0 0.25 pF Input capacitance: command and address CI 1.0 2.0 pF Delta input capacitance: command and address CDI – 0.5 0.5 pF Input/output capacitance: DQ, DQS, DM CIO 1.25 2.5 pF Delta input/output capacitance: DQ, DQS, DM CDIO – 0.6 0.6 pF Notes: Notes 3 3 4 1. This parameter is sampled. VDD/VDDQ = 1.70–1.95V, f = 100 MHz, TA = 25˚C, VOUT(DC) = VDDQ/2, VOUT (peak-to-peak) = 0.2V. DM input is grouped with I/O pins, reflecting the fact that they are matched in loading. 2. This parameter applies to die devices only (does not include package capacitance). 3. The input capacitance per pin group will not differ by more than this maximum amount for any given device. 4. The I/O capacitance per DQS and DQ byte/group will not differ by more than this maximum amount for any given device. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 142 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Electrical Specifications – IDD Parameters Electrical Specifications – IDD Parameters Table 41: IDD Specifications and Conditions, –25°C to +85°C (x16) Notes 1–5 apply to all the parameters/conditions in this table; VDD/VDDQ = 1.70–1.95V Max Parameter/Condition Symbol -5 -54 -6 -75 Unit Notes Operating 1 bank active precharge current: tRC = tRC (MIN); tCK = tCK (MIN); CKE is HIGH; CS is HIGH between valid commands; Address inputs are switching every 2 clock cycles; Data bus inputs are stable IDD0 75 75 75 70 mA 6 Precharge power-down standby current: All banks idle; CKE is LOW; CS is HIGH; tCK = tCK (MIN); Address and control inputs are switching; Data bus inputs are stable IDD2P 900 900 900 900 μA 7, 8 Precharge power-down standby current: Clock stopped; All banks idle; CKE is LOW; CS is HIGH; CK = LOW, CK# = HIGH; Address and control inputs are switching; Data bus inputs are stable IDD2PS 900 900 900 900 μA 7 Precharge nonpower-down standby current: All banks idle; CKE = HIGH; CS = HIGH; tCK = tCK (MIN); Address and control inputs are switching; Data bus inputs are stable IDD2N 15 15 15 12 mA 9 Precharge nonpower-down standby current: Clock stopped; All banks idle; CKE = HIGH; CS = HIGH; CK = LOW, CK# = HIGH; Address and control inputs are switching; Data bus inputs are stable IDD2NS 9 9 8 8 mA 9 Active power-down standby current: 1 bank active; CKE = LOW; CS = HIGH; tCK = tCK (MIN); Address and control inputs are switching; Data bus inputs are stable IDD3P 5 5 5 5 mA 8 Active power-down standby current: Clock stopped; 1 bank active; CKE = LOW; CS = HIGH; CK = LOW; CK# = HIGH; Address and control inputs are switching; Data bus inputs are stable IDD3PS 5 5 5 5 mA Active nonpower-down standby: 1 bank active; CKE = HIGH; CS = HIGH; tCK = tCK (MIN); Address and control inputs are switching; Data bus inputs are stable IDD3N 17 17 16 15 mA 6 Active nonpower-down standby: Clock stopped; 1 bank active; CKE = HIGH; CS = HIGH; CK = LOW; CK# = HIGH; Address and control inputs are switching; Data bus inputs are stable IDD3NS 14 14 13 12 mA 6 Operating burst read: 1 bank active; BL = 4; tCK = tCK (MIN); Continuous READ bursts; Iout = 0mA; Address inputs are switching every 2 clock cycles; 50% data changing each burst IDD4R 90 90 90 90 mA 6 Operating burst write: 1 bank active; BL = 4; tCK = tCK (MIN); Continuous WRITE bursts; Address inputs are switching; 50% data changing each burst IDD4W 90 90 90 90 mA 6 Auto refresh: Burst refresh; CKE = HIGH; Address and control inputs are switching; Data bus inputs are stable tRFC = 138ns IDD5 170 170 170 170 mA 10 tRFC = tREFI IDD5A 12 12 12 12 mA 10, 11 IDD8 10 10 10 10 μA 7, 13 Deep power-down current: Address and control balls are stable; Data bus inputs are stable PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 143 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Electrical Specifications – IDD Parameters Table 42: IDD Specifications and Conditions, –25°C to +85°C (x32) Notes 1–5 apply to all the parameters/conditions in this table; VDD/VDDQ = 1.70–1.95V Max Parameter/Condition Symbol -5 -54 -6 -75 Unit Notes Operating 1 bank active precharge current: tRC = tRC (MIN); tCK = tCK (MIN); CKE is HIGH; CS is HIGH between valid commands; Address inputs are switching every 2 clock cycles; Data bus inputs are stable IDD0 75 75 75 70 mA 6 Precharge power-down standby current: All banks idle; CKE is LOW; CS is HIGH; tCK = tCK (MIN); Address and control inputs are switching; Data bus inputs are stable IDD2P 900 900 900 900 μA 7, 8 Precharge power-down standby current: Clock stopped; All banks idle; CKE is LOW; CS is HIGH, CK = LOW, CK# = HIGH; Address and control inputs are switching; Data bus inputs are stable IDD2PS 900 900 900 900 μA 7 Precharge nonpower-down standby current: All banks idle; CKE = HIGH; CS = HIGH; tCK = tCK (MIN); Address and control inputs are switching; Data bus inputs are stable IDD2N 15 15 15 12 mA 9 Precharge nonpower-down standby current: Clock stopped; All banks idle; CKE = HIGH; CS = HIGH; CK = LOW, CK# = HIGH; Address and control inputs are switching; Data bus inputs are stable IDD2NS 9 9 8 8 mA 9 Active power-down standby current: 1 bank active; CKE = LOW; CS = HIGH; tCK = tCK (MIN); Address and control inputs are switching; Data bus inputs are stable IDD3P 5 5 5 5 mA 8 Active power-down standby current: Clock stopped; 1 bank active; CKE = LOW; CS = HIGH; CK = LOW; CK# = HIGH; Address and control inputs are switching; Data bus inputs are stable IDD3PS 5 5 5 5 mA Active nonpower-down standby: 1 bank active; CKE = HIGH; CS = HIGH; tCK = tCK (MIN); Address and control inputs are switching; Data bus inputs are stable IDD3N 17 17 16 15 mA 6 Active nonpower-down standby: Clock stopped; 1 bank active; CKE = HIGH; CS = HIGH; CK = LOW; CK# = HIGH; Address and control inputs are switching; Data bus inputs are stable IDD3NS 14 14 13 12 mA 6 Operating burst read: 1 bank active; BL = 4; CL = 3; tCK = tCK (MIN); Continuous READ bursts; Iout = 0mA; Address inputs are switching every 2 clock cycles; 50% data changing each burst IDD4R 90 90 90 90 mA 6 Operating burst write: One bank active; BL = 4; tCK = tCK (MIN); Continuous WRITE bursts; Address inputs are switching; 50% data changing each burst IDD4W 90 90 90 90 mA 6 Auto refresh: Burst refresh; CKE = HIGH; Address and control inputs are switching; Data bus inputs are stable tRFC = 138ns IDD5 170 170 170 170 mA 10 tRFC = tREFI IDD5A 12 12 12 12 mA 10, 11 IDD8 10 10 10 10 μA 7, 13 Deep power-down current: Address and control pins are stable; Data bus inputs are stable PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 144 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Electrical Specifications – IDD Parameters Table 43: IDD Specifications and Conditions, –40°C to +105°C (x16) Notes 1–5 apply to all the parameters/conditions in this table; VDD/VDDQ = 1.70–1.95V Max Parameter/Condition Symbol -5 -54 -6 -75 Unit Notes (MIN); Operating 1 bank active precharge current: = tCK (MIN); CKE is HIGH; CS is HIGH between valid commands; Address inputs are switching every 2 clock cycles; Data bus inputs are stable IDD0 100 100 80 70 mA 6 Precharge power-down standby current: All banks idle; CKE is LOW; CS is HIGH; tCK = tCK (MIN); Address and control inputs are switching; Data bus inputs are stable IDD2P 1500 1500 1500 1500 μA 7, 8 Precharge power-down standby current: Clock stopped; All banks idle; CKE is LOW; CS is HIGH; CK = LOW, CK# = HIGH; Address and control inputs are switching; Data bus inputs are stable IDD2PS 1500 1500 1500 1500 μA 7 Precharge nonpower-down standby current: All banks idle; CKE = HIGH; CS = HIGH; tCK = tCK (MIN); Address and control inputs are switching; Data bus inputs are stable IDD2N 19 19 19 16 mA 9 Precharge nonpower-down standby current: Clock stopped; All banks idle; CKE = HIGH; CS = HIGH; CK = LOW, CK# = HIGH; Address and control inputs are switching; Data bus inputs are stable IDD2NS 13 13 12 12 mA 9 Active power-down standby current: 1 bank active; CKE = LOW; CS = HIGH; tCK = tCK (MIN); Address and control inputs are switching; Data bus inputs are stable IDD3P 9 9 9 9 mA 8 Active power-down standby current: Clock stopped; 1 bank active; CKE = LOW; CS = HIGH; CK = LOW; CK# = HIGH; Address and control inputs are switching; Data bus inputs are stable IDD3PS 9 9 9 9 mA Active nonpower-down standby: 1 bank active; CKE = HIGH; CS = HIGH; tCK = tCK (MIN); Address and control inputs are switching; Data bus inputs are stable IDD3N 21 21 20 19 mA 6 Active nonpower-down standby: Clock stopped; 1 bank active; CKE = HIGH; CS = HIGH; CK = LOW; CK# = HIGH; Address and control inputs are switching; Data bus inputs are stable IDD3NS 18 18 17 15 mA 6 Operating burst read: 1 bank active; BL = 4; tCK = tCK (MIN); Continuous READ bursts; Iout = 0mA; Address inputs are switching every 2 clock cycles; 50% data changing each burst IDD4R 130 125 115 105 mA 6 Operating burst write: 1 bank active; BL = 4; tCK = tCK (MIN); Continuous WRITE bursts; Address inputs are switching; 50% data changing each burst IDD4W 130 125 115 105 mA 6 tRC Auto refresh: Burst refresh; CKE = HIGH; Address and control inputs are switching; Data bus inputs are stable = tRC tCK tRFC = 138ns IDD5 170 170 170 170 mA 10 tRFC tREFI IDD5A 13 13 13 13 mA 10, 11 IDD8 15 15 15 15 μA 7, 13 = Deep power-down current: Address and control balls are stable; Data bus inputs are stable PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 145 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Electrical Specifications – IDD Parameters Table 44: IDD Specifications and Conditions, –40°C to +105°C (x32) Notes 1–5 apply to all the parameters/conditions in this table; VDD/VDDQ = 1.70–1.95V Max Parameter/Condition Symbol -5 -54 -6 -75 Unit Notes (MIN); Operating 1 bank active precharge current: = tCK (MIN); CKE is HIGH; CS is HIGH between valid commands; Address inputs are switching every 2 clock cycles; Data bus inputs are stable IDD0 100 100 80 70 mA 6 Precharge power-down standby current: All banks idle; CKE is LOW; CS is HIGH; tCK = tCK (MIN); Address and control inputs are switching; Data bus inputs are stable IDD2P 1500 1500 1500 1500 μA 7, 8 Precharge power-down standby current: Clock stopped; All banks idle; CKE is LOW; CS is HIGH, CK = LOW, CK# = HIGH; Address and control inputs are switching; Data bus inputs are stable IDD2PS 1500 1500 1500 1500 μA 7 Precharge nonpower-down standby current: All banks idle; CKE = HIGH; CS = HIGH; tCK = tCK (MIN); Address and control inputs are switching; Data bus inputs are stable IDD2N 19 19 19 16 mA 9 Precharge nonpower-down standby current: Clock stopped; All banks idle; CKE = HIGH; CS = HIGH; CK = LOW, CK# = HIGH; Address and control inputs are switching; Data bus inputs are stable IDD2NS 13 13 12 12 mA 9 Active power-down standby current: 1 bank active; CKE = LOW; CS = HIGH; tCK = tCK (MIN); Address and control inputs are switching; Data bus inputs are stable IDD3P 9 9 9 9 mA 8 Active power-down standby current: Clock stopped; 1 bank active; CKE = LOW; CS = HIGH; CK = LOW; CK# = HIGH; Address and control inputs are switching; Data bus inputs are stable IDD3PS 9 9 9 9 mA Active nonpower-down standby: 1 bank active; CKE = HIGH; CS = HIGH; tCK = tCK (MIN); Address and control inputs are switching; Data bus inputs are stable IDD3N 21 21 20 19 mA 6 Active nonpower-down standby: Clock stopped; 1 bank active; CKE = HIGH; CS = HIGH; CK = LOW; CK# = HIGH; Address and control inputs are switching; Data bus inputs are stable IDD3NS 18 18 17 15 mA 6 Operating burst read: 1 bank active; BL = 4; CL = 3; tCK = tCK (MIN); Continuous READ bursts; Iout = 0mA; Address inputs are switching every 2 clock cycles; 50% data changing each burst IDD4R 150 145 140 120 mA 6 Operating burst write: One bank active; BL = 4; tCK = tCK (MIN); Continuous WRITE bursts; Address inputs are switching; 50% data changing each burst IDD4W 150 145 140 120 mA 6 tRC Auto refresh: Burst refresh; CKE = HIGH; Address and control inputs are switching; Data bus inputs are stable = tRC tCK tRFC = 138ns IDD5 170 170 170 170 mA 10 tRFC tREFI IDD5A 13 13 13 13 mA 10, 11 IDD8 15 15 15 15 μA 7, 13 = Deep power-down current: Address and control pins are stable; Data bus inputs are stable PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 146 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Electrical Specifications – IDD Parameters Table 45: IDD6 Specifications and Conditions Notes 1–5, 7, and 12 apply to all the parameters/conditions in this table; VDD/VDDQ = 1.70–1.95V Parameter/Condition Symbol Self refresh: CKE = LOW; tCK = tCK (MIN); Address and control inputs are stable; Data bus inputs are stable Notes: Value Units n/a14 μA 2000 μA Full array, 45˚C 900 μA 1/2 array, 85˚C 1450 μA 1/2 array, 45˚C 700 μA 1/4 array, 85˚C 1230 μA Full array, 105˚C Full array, 85˚C IDD6 1/4 array, 45˚C 600 μA 1/8 array, 85˚C 1090 μA 1/8 array, 45˚C 575 μA 1/16 array, 85˚C 1020 μA 1/16 array, 45˚C 550 μA 1. All voltages referenced to VSS. 2. Tests for IDD characteristics may be conducted at nominal supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VDDQ/2 (or to the crossing point for CK/CK#). The output timing reference voltage level is VDDQ/2. 4. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time with the outputs open. 5. IDD specifications are tested after the device is properly initialized and values are averaged at the defined cycle rate. 6. MIN (tRC or tRFC) for IDD measurements is the smallest multiple of tCK that meets the minimum absolute value for the respective parameter. tRASmax for IDD measurements is the largest multiple of tCK that meets the maximum absolute value for tRAS. 7. Measurement is taken 500ms after entering into this operating mode to provide settling time for the tester. 8. VDD must not vary more than 4% if CKE is not active while any bank is active. 9. IDD2N specifies DQ, DQS, and DM to be driven to a valid high or low logic level. 10. CKE must be active (HIGH) during the entire time a REFRESH command is executed. From the time the AUTO REFRESH command is registered, CKE must be active at each rising clock edge until tRFC later. 11. This limit is a nominal value and does not result in a fail. CKE is HIGH during REFRESH command period (tRFC (MIN)) else CKE is LOW (for example, during standby). 12. Values for IDD6 85˚C are guaranteed for the entire temperature range. All other IDD6 values are estimated. 13. Typical values at 25˚C, not a maximum value. 14. Self refresh is not supported for AT (85˚C to 105˚C) operation. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 147 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Electrical Specifications – IDD Parameters Figure 104: Typical Self Refresh Current vs. Temperature 1600 1500 Full Array 1400 1/2 Array 1300 1/4 Array 1/8 Array 1200 1/16 Array Current [μA] 1100 1000 900 800 700 600 500 400 300 200 100 0 –45 –35 –25 –15 –5 5 15 25 35 45 55 65 75 85 Temperature °C PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 148 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Electrical Specifications – AC Operating Conditions Electrical Specifications – AC Operating Conditions Table 46: Electrical Characteristics and Recommended AC Operating Conditions Notes 1–9 apply to all the parameters in this table; VDD/VDDQ = 1.70–1.95V -5 -54 Parameter Access window of DQ from CK/CK# CL = 3 -6 -75 Symbol Min Max Min Max Min Max Min Max Unit tAC 2.0 5.0 2.0 5.0 2.0 5.0 2.0 6.0 ns 2.0 6.5 2.0 6.5 2.0 6.5 2.0 6.5 tCK 5.0 – 5.4 – 6 – 7.5 – 12 – 12 – 12 – 12 – CK high-level width tCH 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK CK low-level width tCL 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK CKE minimum pulse width (high and low) tCKE 1 – 1 – 1 – 1 – tCK 11 Auto precharge write recovery + precharge time tDAL – – – – – – – – – 12 DQ and DM input hold time relative to DQS (fast slew rate) tDH f 0.48 – 0.54 – 0.6 – 0.8 – ns 13, 14, 15 DQ and DM input hold time relative to DQS (slow slew rate) tDH s 0.58 – 0.64 – 0.7 – 0.9 – ns DQ and DM input setup time relative to DQS (fast slew rate) tDS f 0.48 – 0.54 – 0.6 – 0.8 – ns DQ and DM input setup time relative to DQS (slow slew rate) tDS s 0.58 – 0.64 – 0.7 – 0.9 – ns tDIPW 1.8 – 1.9 – 2.1 – 1.8 – ns tDQSCK 2.0 5.0 2.0 5.0 2.0 5.0 2.0 6.0 ns 2.0 6.5 2.0 6.5 2.0 6.5 2.0 6.5 ns Clock cycle time CL = 2 Notes CL = 3 CL = 2 DQ and DM input pulse width (for each input) Access window of DQS from CK/CK# CL = 3 CL = 2 ns DQS input high pulse width tDQSH 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK DQS input low pulse width tDQSL 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK DQS–DQ skew, DQS to last DQ valid, per group, per access tDQSQ – 0.4 – 0.45 – 0.45 – 0.6 ns WRITE command to first DQS latching transition tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 tCK DQS falling edge from CK rising – hold time tDSH 0.2 – 0.2 – 0.2 – 0.2 – tCK DQS falling edge to CK rising – setup time tDSS 0.2 – 0.2 – 0.2 – 0.2 – tCK PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 149 10 13, 14, 15 16 13, 17 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Electrical Specifications – AC Operating Conditions Table 46: Electrical Characteristics and Recommended AC Operating Conditions (Continued) Notes 1–9 apply to all the parameters in this table; VDD/VDDQ = 1.70–1.95V -5 -54 Parameter -6 -75 Symbol Min Max Min Max Min Max Min Max Data valid output window (DVW) n/a tQH tDQSQ tQH tDQSQ tQH tDQSQ tQH tDQSQ Half-clock period tHP tCH, - – tCL Data-out High-Z window from CK/CK# CL = 3 tHZ CL = 2 - tCH, tCH, – tCL - – tCL tCH, - Unit Notes ns 17 – ns 18 19, 20 tCL – 5.0 – 5.0 – 5.5 – 6.0 ns – 6.5 – 6.5 – 6.5 – 6.5 ns Data-out Low-Z window from CK/CK# tLZ 1.0 – 1.0 – 1.0 – 1.0 – ns 19 Address and control input hold time (fast slew rate) tIH F 0.9 – 1.0 – 1.1 – 1.3 – ns 15, 21 Address and control input hold time (slow slew rate) tIH S 1.1 – 1.2 – 1.3 – 1.5 – ns Address and control input setup time (fast slew rate) tIS F 0.9 – 1.0 – 1.1 – 1.3 – ns Address and control input setup time (slow slew rate) tIS S 1.1 – 1.2 – 1.3 – 1.5 – ns Address and control input pulse width tIPW 2.3 – 2.5 – 2.6 – – ns LOAD MODE REGISTER command cycle time tMRD – tCK – ns DQ–DQS hold, DQS to first DQ to go nonvalid, per access tIS + 15, 21 16 tIH tQH 2 tHP – - – tQHS 2 tHP – - 2 tHP – tQHS – - – tQHS 2 tHP - 13, 17 tQHS Data hold skew factor tQHS – 0.5 – 0.5 – 0.65 – 0.75 ns ACTIVE-to-PRECHARGE command tRAS 40 70,000 42 70,000 42 70,000 45 70,000 ns 22 ACTIVE to ACTIVE/ACTIVE to AUTO REFRESH command period tRC 55 – 58.2 – 60 – 67.5 – ns 23 Active to read or write delay tRCD 15 – 16.2 – 18 – 22.5 – ns Refresh period tREF – 64 – 64 – 64 – 64 ms 29 Average periodic refresh interval: 64Mb, 128Mb, and 256Mb (x32) tREFI – 15.6 – 15.6 – 15.6 – 15.6 μs 29 Average periodic refresh interval: 256Mb, 512Mb, 1Gb, 2Gb tREFI – 7.8 – 7.8 – 7.8 – 7.8 μs 29 PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 150 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Electrical Specifications – AC Operating Conditions Table 46: Electrical Characteristics and Recommended AC Operating Conditions (Continued) Notes 1–9 apply to all the parameters in this table; VDD/VDDQ = 1.70–1.95V -5 -54 Parameter -6 -75 Symbol Min Max Min Max Min Max Min Max Unit AUTO REFRESH command period tRFC 72 – 72 – 72 – 72 – ns PRECHARGE command period tRP 15 – 16.2 – 18 – 22.5 – ns DQS read preamble CL = 3 tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 tCK CL = 2 tRPRE 0.5 1.1 0.5 1.1 0.5 1.1 0.5 1.1 tCK DQS read postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK Active bank a to active bank b command tRRD 10 – 10.8 – 12 – 15 – ns Read of SRR to next valid command tSRC CL + 1 – CL + 1 – CL + 1 – CL + 1 – tCK SRR to read tSRR 2 – 2 – 2 – 2 – tCK Internal temperature sensor valid temperature output enable tTQ 2 – 2 – 2 – 2 – ms tWPRE 0.25 – 0.25 – 0.25 – 0.25 – tCK tWPRES 0 – 0 – 0 – 0 – ns 24, 25 tWPST 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK 26 tWR 15 – 15 – 15 – 15 – ns 27 DQS write preamble DQS write preamble setup time DQS write postamble Write recovery time Internal WRITE-to-READ command delay Exit power-down mode to first valid command Exit self refresh to first valid command Notes: tWTR 2 – 2 – 1 – 1 – tCK tXP 2 – 2 – 1 – 1 – tCK tXSR 112.5 – 112.5 – 112.5 – 112.5 – ns Notes 28 1. All voltages referenced to VSS. 2. All parameters assume proper device initialization. 3. Tests for AC timing and electrical AC and DC characteristics may be conducted at nominal supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage ranges specified. 4. The circuit shown below represents the timing reference load used in defining the relevant timing parameters of the device. It is not intended to be either a precise representation of the typical system environment or a depiction of the actual load presented by a production tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to system environment. Specifications are correlated to production test conditions (generally a coaxial transmission line terminated at the tester electronics). For the half-strength driver with a nominal 10pF load, parameters tAC and tQH are expected to be in the same range. However, these parameters are not subject to production test but are estimated by design/characterization. Use of IBIS or other simu- PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 151 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Electrical Specifications – AC Operating Conditions lation tools for system design validation is suggested. 50 50 I/O I/O 10pF 20pF Full drive strength Half drive strength 5. The CK/CK# input reference voltage level (for timing referenced to CK/CK#) is the point at which CK and CK# cross; the input reference voltage level for signals other than CK/CK# is VDDQ/2. 6. A CK and CK# input slew rate ≥1 V/ns (2 V/ns if measured differentially) is assumed for all parameters. 7. All AC timings assume an input slew rate of 1 V/ns. 8. CAS latency definition: with CL = 2, the first data element is valid at (tCK + tAC) after the clock at which the READ command was registered; for CL = 3, the first data element is valid at (2 × tCK + tAC) after the first clock at which the READ command was registered. 9. Timing tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VDDQ/2 or to the crossing point for CK/CK#. The output timing reference voltage level is VDDQ/2. 10. Clock frequency change is only permitted during clock stop, power-down, or self refresh mode. 11. In cases where the device is in self refresh mode for tCKE, tCKE starts at the rising edge of the clock and ends when CKE transitions HIGH. t 12. DAL = (tWR/tCK) + (tRP/tCK): for each term, if not already an integer, round up to the next highest integer. 13. Referenced to each output group: for x16, LDQS with DQ[7:0]; and UDQS with DQ[15:8]. For x32, DQS0 with DQ[7:0]; DQS1 with DQ[15:8]; DQS2 with DQ[23:16]; and DQS3 with DQ[31:24]. 14. DQ and DM input slew rates must not deviate from DQS by more than 10%. If the DQ/DM/DQS slew rate is less than 1.0 V/ns, timing must be derated: 50ps must be added to tDS and tDH for each 100 mV/ns reduction in slew rate. If the slew rate exceeds 4 V/ns, functionality is uncertain. 15. The transition time for input signals (CAS#, CKE, CS#, DM, DQ, DQS, RAS#, WE#, and addresses) are measured between VIL(DC) to VIH(AC) for rising input signals and VIH(DC) to VIL(AC) for falling input signals. 16. These parameters guarantee device timing but are not tested on each device. 17. The valid data window is derived by achieving other specifications: tHP (tCK/2), tDQSQ, and tQH (tHP - tQHS). The data valid window derates directly proportional with the clock duty cycle and a practical data valid window can be derived. The clock is provided a maximum duty cycle variation of 45/55. Functionality is uncertain when operating beyond a 45/55 ratio. 18. tHP (MIN) is the lesser of tCL (MIN) and tCH (MIN) actually applied to the device CK and CK# inputs, collectively. 19. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (tHZ) or begins driving (tLZ). 20. tHZ (MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition. 21. Fast command/address input slew rate ≥1 V/ns. Slow command/address input slew rate ≥0.5 V/ns. If the slew rate is less than 0.5 V/ns, timing must be derated: tIS has an additional 50ps per each 100 mV/ns reduction in slew rate from the 0.5 V/ns. tIH has 0ps added, therefore, it remains constant. If the slew rate exceeds 4.5 V/ns, functionality is uncertain. 22. READs and WRITEs with auto precharge must not be issued until tRAS (MIN) can be satisfied prior to the internal PRECHARGE command being issued. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 152 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Electrical Specifications – AC Operating Conditions 23. DRAM devices should be evenly addressed when being accessed. Disproportionate accesses to a particular row address may result in reduction of the product lifetime. 24. This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turnaround. 25. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS going from High-Z to logic low) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be HIGH during this time, depending on tDQSS. 26. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 27. At least 1 clock cycle is required during tWR time when in auto precharge mode. 28. Clock must be toggled a minimum of two times during the tXSR period. 29. For the Automotive Temperature parts, tREF = tREF /2 and tREF I = tREF I/2 . PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 153 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Output Drive Characteristics Output Drive Characteristics Table 47: Target Output Drive Characteristics (Full Strength) Notes 1–2 apply to all values; characteristics are specified under best and worst process variations/conditions Pull-Down Current (mA) Pull-Up Current (mA) Voltage (V) Min Max Min Max 0.00 0.00 0.00 0.00 0.00 0.10 2.80 18.53 –2.80 –18.53 0.20 5.60 26.80 –5.60 –26.80 0.30 8.40 32.80 –8.40 –32.80 0.40 11.20 37.05 –11.20 –37.05 0.50 14.00 40.00 –14.00 –40.00 0.60 16.80 42.50 –16.80 –42.50 0.70 19.60 44.57 –19.60 –44.57 0.80 22.40 46.50 –22.40 –46.50 0.85 23.80 47.48 –23.80 –47.48 0.90 23.80 48.50 –23.80 –48.50 0.95 23.80 49.40 –23.80 –49.40 1.00 23.80 50.05 –23.80 –50.05 1.10 23.80 51.35 –23.80 –51.35 1.20 23.80 52.65 –23.80 –52.65 1.30 23.80 53.95 –23.80 –53.95 1.40 23.80 55.25 –23.80 –55.25 1.50 23.80 56.55 –23.80 –56.55 1.60 23.80 57.85 –23.80 –57.85 1.70 23.80 59.15 –23.80 –59.15 1.80 – 60.45 – –60.45 1.90 – 61.75 – –61.75 Notes: 1. Based on nominal impedance of 25Ω (full strength) at VDDQ/2. 2. The full variation in driver current from minimum to maximum, due to process, voltage, and temperature, will lie within the outer bounding lines of the I-V curves. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 154 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Output Drive Characteristics Table 48: Target Output Drive Characteristics (Three-Quarter Strength) Notes 1–3 apply to all values; characteristics are specified under best and worst process variations/conditions Pull-Down Current (mA) Pull-Up Current (mA) Voltage (V) Min Max Min Max 0.00 0.00 0.00 0.00 0.00 0.10 1.96 12.97 –1.96 –12.97 0.20 3.92 18.76 –3.92 –18.76 0.30 5.88 22.96 –5.88 –22.96 0.40 7.84 25.94 –7.84 –25.94 0.50 9.80 28.00 –9.80 –28.00 0.60 11.76 29.75 –11.76 –29.75 0.70 13.72 31.20 –13.72 –31.20 0.80 15.68 32.55 –15.68 –32.55 0.85 16.66 33.24 –16.66 –33.24 0.90 16.66 33.95 –16.66 –33.95 0.95 16.66 34.58 –16.66 –34.58 1.00 16.66 35.04 –16.66 –35.04 1.10 16.66 35.95 –16.66 –35.95 1.20 16.66 36.86 –16.66 –36.86 1.30 16.66 37.77 –16.66 –37.77 1.40 16.66 38.68 –16.66 –38.68 1.50 16.66 39.59 –16.66 –39.59 1.60 16.66 40.50 –16.66 –40.50 1.70 16.66 41.41 –16.66 –41.41 1.80 – 42.32 – –42.32 1.90 – 43.23 – –43.23 Notes: 1. Based on nominal impedance of 37Ω (three-quarter drive strength) at VDDQ/2. 2. The full variation in driver current from minimum to maximum, due to process, voltage, and temperature, will lie within the outer bounding lines of the I-V curves. 3. Contact factory for availability of three-quarter drive strength. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 155 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Output Drive Characteristics Table 49: Target Output Drive Characteristics (One-Half Strength) Notes 1–3 apply to all values; characteristics are specified under best and worst process variations/conditions Pull-Down Current (mA) Pull-Up Current (mA) Voltage (V) Min Max Min Max 0.00 0.00 0.00 0.00 0.00 0.10 1.27 8.42 –1.27 –8.42 0.20 2.55 12.30 –2.55 –12.30 0.30 3.82 14.95 –3.82 –14.95 0.40 5.09 16.84 –5.09 –16.84 0.50 6.36 18.20 –6.36 –18.20 0.60 7.64 19.30 –7.64 –19.30 0.70 8.91 20.30 –8.91 –20.30 0.80 10.16 21.20 –10.16 –21.20 0.85 10.80 21.60 –10.80 –21.60 0.90 10.80 22.00 –10.80 –22.00 0.95 10.80 22.45 –10.80 –22.45 1.00 10.80 22.73 –10.80 –22.73 1.10 10.80 23.21 –10.80 –23.21 1.20 10.80 23.67 –10.80 –23.67 1.30 10.80 24.14 –10.80 –24.14 1.40 10.80 24.61 –10.80 –24.61 1.50 10.80 25.08 –10.80 –25.08 1.60 10.80 25.54 –10.80 –25.54 1.70 10.80 26.01 –10.80 –26.01 1.80 – 26.48 – –26.48 1.90 – 26.95 – –26.95 Notes: 1. Based on nominal impedance of 55Ω (one-half drive strength) at VDDQ/2. 2. The full variation in driver current from minimum to maximum, due to process, voltage, and temperature, will lie within the outer bounding lines of the I-V curves. 3. The I-V curve for one-quarter drive strength is approximately 50% of one-half drive strength. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 156 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Functional Description Functional Description The Mobile LPDDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O. Single read or write access for the device consists of a single 2n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n-bit-wide, one-half-clockcycle data transfers at the I/O. A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the device during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. The x16 device has two data strobes, one for the lower byte and one for the upper byte; the x32 device has four data strobes, one per byte. The LPDDR device operates from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Read and write accesses to the device are burst-oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. The device provides for programmable READ or WRITE burst lengths of 2, 4, 8, or 16. An auto precharge function can be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard DDR SDRAM, the pipelined, multibank architecture of LPDDR supports concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. An auto refresh mode is provided, along with a power-saving power-down mode. Deep power-down mode is offered to achieve maximum power reduction by eliminating the power of the memory array. Data will not be retained after the device enters deep power-down mode. Two self refresh features, temperature-compensated self refresh (TCSR) and partial-array self refresh (PASR), offer additional power savings. TCSR is controlled by the automatic on-chip temperature sensor. PASR can be customized using the extended mode register settings. The two features can be combined to achieve even greater power savings. The DLL that is typically used on standard DDR devices is not necessary on LPDDR devices. It has been omitted to save power. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 157 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Commands Commands A quick reference for available commands is provided in Table 50 and Table 51 (page 159), followed by a written description of each command. Three additional truth tables (Table 52 (page 165), Table 53 (page 167), and Table 54 (page 169)) provide CKE commands and current/next state information. Table 50: Truth Table – Commands CKE is HIGH for all commands shown except SELF REFRESH and DEEP POWER-DOWN; all states and sequences not shown are reserved and/or illegal Name (Function) CS# RAS# CAS# WE# Address Notes DESELECT (NOP) H X X X X 1 NO OPERATION (NOP) L H H ACTIVE (select bank and activate row) L L H H X 1 H Bank/row 2 READ (select bank and column, and start READ burst) L H L H Bank/column 3 WRITE (select bank and column, and start WRITE burst) L H L L Bank/column 3 BURST TERMINATE or DEEP POWER-DOWN (enter deep power-down mode) L H H L X 4, 5 PRECHARGE (deactivate row in bank or banks) L L H L Code 6 AUTO REFRESH (refresh all or single bank) or SELF REFRESH (enter self refresh mode) L L L H X 7, 8 LOAD MODE REGISTER L L L L Op-code 9 Notes: 1. DESELECT and NOP are functionally interchangeable. 2. BA0–BA1 provide bank address and A[0:I] provide row address (where I = the most significant address bit for each configuration). 3. BA0–BA1 provide bank address; A[0:I] provide column address (where I = the most significant address bit for each configuration); A10 HIGH enables the auto precharge feature (nonpersistent); A10 LOW disables the auto precharge feature. 4. Applies only to READ bursts with auto precharge disabled; this command is undefined and should not be used for READ bursts with auto precharge enabled and for WRITE bursts. 5. This command is a BURST TERMINATE if CKE is HIGH and DEEP POWER-DOWN if CKE is LOW. 6. A10 LOW: BA0–BA1 determine which bank is precharged. A10 HIGH: all banks are precharged and BA0–BA1 are “Don’t Care.” 7. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. 8. Internal refresh counter controls row addressing; in self refresh mode all inputs and I/Os are “Don’t Care” except for CKE. 9. BA0–BA1 select the standard mode register, extended mode register, or status register. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 158 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Commands Table 51: DM Operation Truth Table Name (Function) Notes: DM DQ Notes Write enable L Valid 1, 2 Write inhibit H X 1, 2 1. Used to mask write data; provided coincident with the corresponding data. 2. All states and sequences not shown are reserved and/or illegal. DESELECT The DESELECT function (CS# HIGH) prevents new commands from being executed by the device. Operations already in progress are not affected. NO OPERATION The NO OPERATION (NOP) command is used to instruct the selected device to perform a NOP. This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. LOAD MODE REGISTER The mode registers are loaded via inputs A[0:n]. See mode register descriptions in Standard Mode Register and Extended Mode Register. The LOAD MODE REGISTER command can only be issued when all banks are idle, and a subsequent executable command cannot be issued until tMRD is met. ACTIVE The ACTIVE command is used to activate a row in a particular bank for a subsequent access. The values on the BA0 and BA1 inputs select the bank, and the address provided on inputs A[0:n] selects the row. This row remains active for accesses until a PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 159 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Commands Figure 105: ACTIVE Command CK# CK CKE HIGH CS# RAS# CAS# WE# Address Row BA0, BA1 Bank Don’t Care READ The READ command is used to initiate a burst read access to an active row. The values on the BA0 and BA1 inputs select the bank; the address provided on inputs A[I:0] (where I = the most significant column address bit for each configuration) selects the starting column location. The value on input A10 determines whether auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the READ burst; if auto precharge is not selected, the row will remain open for subsequent accesses. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 160 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Commands Figure 106: READ Command CK# CK CKE HIGH CS# RAS# CAS# WE# Address Column EN AP A10 DIS AP BA0, BA1 Bank Don’t Care Note: 1. EN AP = enable auto precharge; DIS AP = disable auto precharge. WRITE The WRITE command is used to initiate a burst write access to an active row. The values on the BA0 and BA1 inputs select the bank; the address provided on inputs A[I:0] (where I = the most significant column address bit for each configuration) selects the starting column location. The value on input A10 determines whether auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the WRITE burst; if auto precharge is not selected, the row will remain open for subsequent accesses. Input data appearing on the DQ is written to the memory array, subject to the DM input logic level appearing coincident with the data. If a given DM signal is registered LOW, the corresponding data will be written to memory; if the DM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that byte/column location. If a WRITE or a READ is in progress, the entire data burst must be complete prior to stopping the clock (see Clock Change Frequency (page 219)). A burst completion for WRITEs is defined when the write postamble and tWR or tWTR are satisfied. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 161 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Commands Figure 107: WRITE Command CK# CK CKE HIGH CS# RAS# CAS# WE# Address Column EN AP A10 DIS AP BA0, BA1 Bank Don’t Care Note: 1. EN AP = enable auto precharge; DIS AP = disable auto precharge. PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the PRECHARGE command is issued. Input A10 determines whether one or all banks will be precharged, and in the case where only one bank is precharged, inputs BA0 and BA1 select the bank. Otherwise, BA0 and BA1 are treated as “Don’t Care.” After a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 162 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Commands Figure 108: PRECHARGE Command CK# CK CKE HIGH CS# RAS# CAS# WE# Address All banks A10 Single bank BA0, BA1 Bank Don’t Care Note: 1. If A10 is HIGH, bank address becomes “Don’t Care.” BURST TERMINATE The BURST TERMINATE command is used to truncate READ bursts with auto precharge disabled. The most recently registered READ command prior to the BURST TERMINATE command will be truncated, as described in READ Operation. The open page from which the READ was terminated remains open. AUTO REFRESH AUTO REFRESH is used during normal operation of the device and is analogous to CAS#-BEFORE-RAS# (CBR) REFRESH in FPM/EDO DRAM. The AUTO REFRESH command is nonpersistent and must be issued each time a refresh is required. Addressing is generated by the internal refresh controller. This makes the address bits a “Don’t Care” during an AUTO REFRESH command. For improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. The auto refresh period begins when the AUTO REFRESH command is registered and ends tRFC later. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 163 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Commands SELF REFRESH The SELF REFRESH command is used to place the device in self refresh mode; self refresh mode is used to retain data in the memory device while the rest of the system is powered down. When in self refresh mode, the device retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command, except that CKE is disabled (LOW). After the SELF REFRESH command is registered, all inputs to the device become “Don’t Care” with the exception of CKE, which must remain LOW. Micron recommends that, prior to self refresh entry and immediately upon self refresh exit, the user perform a burst auto refresh cycle for the number of refresh rows. Alternatively, if a distributed refresh pattern is used, this pattern should be immediately resumed upon self refresh exit. DEEP POWER-DOWN The DEEP POWER-DOWN (DPD) command is used to enter DPD mode, which achieves maximum power reduction by eliminating the power to the memory array. Data will not be retained when the device enters DPD mode. The DPD command is the same as a BURST TERMINATE command with CKE LOW. Figure 109: DEEP POWER-DOWN Command CK# CK CKE CS# RAS# CAS# WE# Address BA0, BA1 Don’t Care PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 164 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Truth Tables Truth Tables Table 52: Truth Table – Current State Bank n – Command to Bank n Notes 1–6 apply to all parameters in this table Current State CS# RAS# CAS# WE# Any Idle Row active Read (auto precharge disabled) Write (auto precharge disabled) Command/Action Notes H X X X DESELECT (NOP/continue previous operation) L H H H NO OPERATION (NOP/continue previous operation) L L H H ACTIVE (select and activate row) L L L H AUTO REFRESH L L L L LOAD MODE REGISTER 7 L H L H READ (select column and start READ burst) 10 L H L L WRITE (select column and start WRITE burst) 10 L L H L PRECHARGE (deactivate row in bank or banks) 8 L H L H READ (select column and start new READ burst) L H L L WRITE (select column and start WRITE burst) L L H L PRECHARGE (truncate READ burst, start PRECHARGE) 8 L H H L BURST TERMINATE 9 L H L H READ (select column and start READ burst) L H L L WRITE (select column and start new WRITE burst) L L H L PRECHARGE (truncate WRITE burst, start PRECHARGE) Notes: 7 10 10, 12 10, 11 10 8, 11 1. This table applies when CKEn - 1 was HIGH, CKEn is HIGH and after tXSR has been met (if the previous state was self refresh), after tXP has been met (if the previous state was power-down), or after a full initialization (if the previous state was deep power-down). 2. This table is bank-specific, except where noted (for example, the current state is for a specific bank and the commands shown are supported for that bank when in that state). Exceptions are covered in the notes below. 3. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated with auto precharge disabled and has not yet terminated or been terminated. Write: A WRITE burst has been initiated with auto precharge disabled and has not yet terminated or been terminated. 4. The states listed below must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands, or supported commands to the other bank, must be issued on any clock edge occurring during these states. Supported commands to any other bank are determined by that bank’s current state. Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met. After tRP is met, the bank will be in the idle state. Row activating: Starts with registration of an ACTIVE command and ends when tRCD is met. After tRCD is met, the bank will be in the row active state. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 165 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Truth Tables Read with auto-precharge enabled: Starts with registration of a READ command with auto precharge enabled and ends when tRP has been met. After tRP is met, the bank will be in the idle state. Write with auto-precharge enabled: Starts with registration of a WRITE command with auto precharge enabled and ends when tRP has been met. After tRP is met, the bank will be in the idle state. 5. The states listed below must not be interrupted by any executable command; DESELECT or NOP commands must be applied on each positive clock edge during these states. Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRFC is met. After tRFC is met, the device will be in the all banks idle state. Accessing mode register: Starts with registration of a LOAD MODE REGISTER command and ends when tMRD has been met. After tMRD is met, the device will be in the all banks idle state. Precharging all: Starts with registration of a PRECHARGE ALL command and ends when is met. After tRP is met, all banks will be in the idle state. All states and sequences not shown are illegal or reserved. Not bank-specific; requires that all banks are idle, and bursts are not in progress. May or may not be bank-specific; if multiple banks need to be precharged, each must be in a valid state for precharging. Not bank-specific; BURST TERMINATE affects the most recent READ burst, regardless of bank. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. Requires appropriate DM masking. A WRITE command can be applied after the completion of the READ burst; otherwise, a BURST TERMINATE must be used to end the READ burst prior to asserting a WRITE command. tRP 6. 7. 8. 9. 10. 11. 12. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 166 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Truth Tables Table 53: Truth Table – Current State Bank n – Command to Bank m Notes 1–6 apply to all parameters in this table Current State CS# RAS# CAS# WE# Any Command/Action Notes H X X X DESELECT (NOP/continue previous operation) L H H H NO OPERATION (NOP/continue previous operation) Idle X X X X Any command supported to bank m Row activating, active, or precharging L L H H ACTIVE (select and activate row) L H L H READ (select column and start READ burst) L H L L WRITE (select column and start WRITE burst) L L H L PRECHARGE L L H H ACTIVE (select and activate row) L H L H READ (select column and start new READ burst) L H L L WRITE (select column and start WRITE burst) L L H L PRECHARGE L L H H ACTIVE (select and activate row) L H L H READ (select column and start READ burst) L H L L WRITE (select column and start new WRITE burst) L L H L PRECHARGE L L H H ACTIVE (select and activate row) L H L H READ (select column and start new READ burst) L H L L WRITE (select column and start WRITE burst) L L H L PRECHARGE L L H H ACTIVE (select and activate row) L H L H READ (select column and start READ burst) L H L L WRITE (select column and start new WRITE burst) L L H L PRECHARGE Notes: 1. This table applies when CKEn - 1 was HIGH, CKEn is HIGH and after tXSR has been met (if the previous state was self refresh), after tXP has been met (if the previous state was power-down) or after a full initialization (if the previous state was deep power-down). 2. This table describes alternate bank operation, except where noted (for example, the current state is for bank n and the commands shown are those supported for issue to bank m, assuming that bank m is in such a state that the given command is supported). Exceptions are covered in the notes below. 3. Current state definitions: Read (auto precharge disabled) Write (auto precharge disabled) Read (with auto precharge) Write (with auto precharge) 7 7 Idle: The bank has been precharged, and tRP has been met. Row active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated and has not yet terminated or been terminated. Write: A WRITE burst has been initiated and has not yet terminated or been terminated. 3a. Both the read with auto precharge enabled state or the write with auto precharge enabled state can be broken into two parts: the access period and the precharge period. For read with auto precharge, the precharge period is defined as if the same burst was PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 167 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Truth Tables executed with auto precharge disabled and then followed with the earliest possible PRECHARGE command that still accesses all of the data in the burst. For write with auto precharge, the precharge period begins when tWR ends, with tWR measured as if auto precharge was disabled. The access period starts with registration of the command and ends when the precharge period (or tRP) begins. This device supports concurrent auto precharge such that when a read with auto precharge is enabled or a write with auto precharge is enabled, any command to other banks is supported, as long as that command does not interrupt the read or write data transfer already in process. In either case, all other related limitations apply (i.e., contention between read data and write data must be avoided). 3b. The minimum delay from a READ or WRITE command (with auto precharge enabled) to a command to a different bank is summarized below. From Command Minimum Delay (with Concurrent Auto Precharge) To Command WRITE with Auto Precharge READ or READ with auto precharge WRITE or WRITE with auto precharge PRECHARGE ACTIVE [1 + (BL/2)] tCK + tWTR (BL/2) tCK 1 tCK 1 tCK READ with Auto Precharge READ or READ with auto precharge WRITE or WRITE with auto precharge PRECHARGE ACTIVE (BL/2) × tCK [CL + (BL/2)] tCK 1 tCK 1 tCK 4. AUTO REFRESH and LOAD MODE REGISTER commands can only be issued when all banks are idle. 5. All states and sequences not shown are illegal or reserved. 6. Requires appropriate DM masking. 7. A WRITE command can be applied after the completion of the READ burst; otherwise, a BURST TERMINATE must be used to end the READ burst prior to asserting a WRITE command. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 168 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Truth Tables Table 54: Truth Table – CKE Notes 1–4 apply to all parameters in this table Current State CKEn - 1 CKEn COMMANDn ACTIONn Notes Active power-down L L X Maintain active power-down Deep power-down L L X Maintain deep power-down Precharge power-down L L X Maintain precharge power-down Self refresh L L X Maintain self refresh Active power-down L H DESELECT or NOP Exit active power-down 5 Deep power-down L H DESELECT or NOP Exit deep power-down 6 Precharge power-down L H DESELECT or NOP Exit precharge power-down Self refresh L H DESELECT or NOP Exit self refresh Bank(s) active H L DESELECT or NOP Active power-down entry All banks idle H L BURST TERMINATE Deep power-down entry All banks idle H L DESELECT or NOP Precharge power-down entry All banks idle H L AUTO REFRESH Self refresh entry H H See Table 53 (page 167) H H See Table 53 (page 167) Notes: 5, 7 1. CKEn is the logic state of CKE at clock edge n; CKEn - 1 was the state of CKE at the previous clock edge. 2. Current state is the state of the DDR SDRAM immediately prior to clock edge n. 3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COMMANDn. 4. All states and sequences not shown are illegal or reserved. 5. DESELECT or NOP commands should be issued on each clock edge occurring during the tXP or tXSR period. 6. After exiting deep power-down mode, a full DRAM initialization sequence is required. 7. The clock must toggle at least two times during the tXSR period. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 169 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP State Diagram State Diagram Figure 110: Simplified State Diagram Power applied Power on Self refresh DPDX PRE Deep powerdown PREALL SRR Idle: all banks precharged LMR LMR EMR READ SRR DPD LMR READ SREFX SREF Auto refresh AREF CKEL CKEH Active powerdown Precharge powerdown ACT CKEH CKEL Row active Burst terminate READ WRITE BST WRITE WRITE A READ READ A READ WRITING READING WRITE WRITE A WRITING PRE READ A WRITE A PRE READ A PRE PRE READING Precharging Automatic sequence Command sequence ACT = ACTIVE AREF = AUTO REFRESH BST = BURST TERMINATE CKEH = Exit power-down CKEL = Enter power-down DPD = Enter deep power-down PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 DPDX = Exit deep power-down EMR = LOAD EXTENDED MODE REGISTER LMR = LOAD MODE REGISTER PRE = PRECHARGE PREALL = PRECHARGE all banks READ = READ w/o auto precharge 170 READ A = READ w/ auto precharge SREF = Enter self refresh SREFX = Exit self refresh SRR = STATUS REGISTER READ WRITE = WRITE w/o auto precharge WRITE A = WRITE w/ auto precharge Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Initialization Initialization Prior to normal operation, the device must be powered up and initialized in a predefined manner. Using initialization procedures other than those specified will result in undefined operation. If there is an interruption to the device power, the device must be re-initialized using the initialization sequence described below to ensure proper functionality of the device. To properly initialize the device, this sequence must be followed: 1. The core power (VDD) and I/O power (VDDQ) must be brought up simultaneously. It is recommended that V DD and V DDQ be from the same power source, or V DDQ must never exceed V DD. Standard initialization requires that CKE be asserted HIGH (see Figure 111 (page 172)). Alternatively, initialization can be completed with CKE LOW provided that CKE transitions HIGH tIS prior to T0 (see Figure 112 (page 173)). 2. When power supply voltages are stable and the CKE has been driven HIGH, it is safe to apply the clock. 3. When the clock is stable, a 200μs minimum delay is required by the Mobile LPDDR prior to applying an executable command. During this time, NOP or DESELECT commands must be issued on the command bus. 4. Issue a PRECHARGE ALL command. 5. Issue NOP or DESELECT commands for at least tRP time. 6. Issue an AUTO REFRESH command followed by NOP or DESELECT commands for at least tRFC time. Issue a second AUTO REFRESH command followed by NOP or DESELECT commands for at least tRFC time. Two AUTO REFRESH commands must be issued. Typically, both of these commands are issued at this stage as described above. 7. Using the LOAD MODE REGISTER command, load the standard mode register as desired. 8. Issue NOP or DESELECT commands for at least tMRD time. 9. Using the LOAD MODE REGISTER command, load the extended mode register to the desired operating modes. Note that the sequence in which the standard and extended mode registers are programmed is not critical. 10. Issue NOP or DESELECT commands for at least tMRD time. After steps 1–10 are completed, the device has been properly initialized and is ready to receive any valid command. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 171 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Initialization Figure 111: Initialize and Load Mode Registers (( )) VDD (( )) VDDQ T1 T0 CK# (( )) (( )) CK LVCMOS HIGH LEVEL CKE (( )) (( )) Command1 (( )) (( )) tCH tIS NOP2 tCL Ta0 Tb0 Tc0 Td0 Te0 Tf0 (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) tIH NOP PRE tCK (( )) (( )) AR (( )) (( )) AR (( )) (( )) LMR (( )) (( )) LMR (( )) (( )) ACT3 (( )) (( )) DM (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) Address (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) A10 (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) BA0, BA1 (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) DQS (( )) High-Z (( )) (( )) (( )) (( )) (( )) (( )) DQ (( )) High-Z (( )) (( )) (( )) (( )) (( )) (( )) tRFC4 tRFC4 tMRD4 (( )) (( )) tIS All banks tIS T = 200μs tIH tRP4 Power-up: VDD and CK stable Notes: (( )) (( )) Op-code (( )) (( )) Row (( )) (( )) (( )) (( )) Op-code (( )) (( )) Row (( )) (( )) (( )) (( )) BA0 = L, BA1 = H (( )) (( )) Bank (( )) (( )) tIH Op-code tIS (( )) (( )) tIH Op-code tIS (( )) (( )) NOP3 tIH BA0 = L, BA1 = L Load standard mode register tMRD4 Load extended mode register Don’t Care 1. PRE = PRECHARGE command; LMR = LOAD MODE REGISTER command; AR = AUTO REFRESH command; ACT = ACTIVE command. 2. NOP or DESELECT commands are required for at least 200μs. 3. Other valid commands are possible. 4. NOPs or DESELECTs are required during this time. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 172 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Initialization Figure 112: Alternate Initialization with CKE LOW (( )) VDD (( )) VDDQ T1 T0 CK# (( )) (( )) CK tCH tCL Ta0 Tb0 Tc0 Td0 Te0 Tf0 (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) tIS CKE 1 Command LVCMOS LOW level 2 NOP (( )) (( )) (( )) (( )) tIS tIH NOP PRE (( )) (( )) AR (( )) (( )) AR (( )) (( )) LMR (( )) (( )) LMR (( )) (( )) ACT3 (( )) (( )) NOP3 T = 200μs Don’t Care Power up: VDD and CK stable Notes: 1. PRE = PRECHARGE command; LMR = LOAD MODE REGISTER command; AR = AUTO REFRESH command; ACT = ACTIVE command. 2. NOP or DESELECT commands are required for at least 200μs. 3. Other valid commands are possible. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 173 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Standard Mode Register Standard Mode Register The standard mode register bit definition enables the selection of burst length, burst type, CAS latency (CL), and operating mode, as shown in Figure 113. Reserved states should not be used as this may result in setting the device into an unknown state or cause incompatibility with future versions of LPDDR devices. The standard mode register is programmed via the LOAD MODE REGISTER command (with BA0 = 0 and BA1 = 0) and will retain the stored information until it is programmed again, until the device goes into deep power-down mode, or until the device loses power. Reprogramming the mode register will not alter the contents of the memory, provided it is performed correctly. The mode register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait tMRD before initiating the subsequent operation. Violating any of these requirements will result in unspecified operation. Figure 113: Standard Mode Register Definition BA1 BA0 An ... A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 n + 2 n + 1 n ... 10 9 8 Operating Mode 0 0 7 6 5 4 3 2 1 0 CAS Latency BT Burst Length Standard mode register (Mx) Burst Length Mn + 2 Mn + 1 Mode Register Definition 0 0 Standard mode register 0 1 Status register 0 0 1 0 Extended mode register 0 1 1 Reserved 0 M2 M1 M0 M3 = 0 M3 = 1 0 Reserved Reserved 0 1 2 2 1 0 4 4 0 1 1 8 8 1 0 0 16 16 1 0 1 Reserved Reserved 0 0 0 0 0 Normal operation 1 1 0 Reserved Reserved – – – – – All other states reserved 1 1 1 Reserved Reserved Mn ... M10 M9 M8 M7 Operating Mode M6 M5 M4 0 Note: Address bus 0 0 Burst Type CAS Latency M3 Reserved 0 Sequential 1 Interleaved 0 0 1 Reserved 0 1 0 2 0 1 1 3 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved 1. The integer n is equal to the most significant address bit. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 174 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Standard Mode Register Burst Length Read and write accesses to the device are burst-oriented, and the burst length (BL) is programmable. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 2, 4, 8, or 16 locations are available for both sequential and interleaved burst types. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap when a boundary is reached. The block is uniquely selected by A[i:1] when BL = 2, by A[i:2] when BL = 4, by A[i:3] when BL = 8, and by A[i:4] when BL = 16, where Ai is the most significant column address bit for a given configuration. The remaining (least significant) address bits are used to specify the starting location within the block. The programmed burst length applies to both READ and WRITE bursts. Burst Type Accesses within a given burst can be programmed to be either sequential or interleaved via the standard mode register. The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address. Table 55: Burst Definition Table Burst Length Order of Accesses Within a Burst Starting Column Address 2 Type = Interleaved 0 0-1 0-1 1 1-0 1-0 A0 4 8 16 Type = Sequential A3 A1 A0 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 A2 A1 A0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 1 1 1 A2 A1 A0 PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 175 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Standard Mode Register Table 55: Burst Definition Table (Continued) Burst Length Order of Accesses Within a Burst Starting Column Address Type = Sequential Type = Interleaved 0 0 0 0 0-1-2-3-4-5-6-7-8-9-A-B-C-D-E-F 0-1-2-3-4-5-6-7-8-9-A-B-C-D-E-F 0 0 0 1 1-2-3-4-5-6-7-8-9-A-B-C-D-E-F-0 1-0-3-2-5-4-7-6-9-8-B-A-D-C-F-E 0 0 1 0 2-3-4-5-6-7-8-9-A-B-C-D-E-F-0-1 2-3-0-1-6-7-4-5-A-B-8-9-E-F-C-D 0 0 1 1 3-4-5-6-7-8-9-A-B-C-D-E-F-0-1-2 3-2-1-0-7-6-5-4-B-A-9-8-F-E-D-C 0 1 0 0 4-5-6-7-8-9-A-B-C-D-E-F-0-1-2-3 4-5-6-7-0-1-2-3-C-D-E-F-8-9-A-B 0 1 0 1 5-6-7-8-9-A-B-C-D-E-F-0-1-2-3-4 5-4-7-6-1-0-3-2-D-C-F-E-9-8-B-A 0 1 1 0 6-7-8-9-A-B-C-D-E-F-0-1-2-3-4-5 6-7-4-5-2-3-0-1-E-F-C-D-A-B-8-9 0 1 1 1 7-8-9-A-B-C-D-E-F-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0-F-E-D-C-B-A-9-8 1 0 0 0 8-9-A-B-C-D-E-F-0-1-2-3-4-5-6-7 8-9-A-B-C-D-E-F-0-1-2-3-4-5-6-7 1 0 0 1 9-A-B-C-D-E-F-0-1-2-3-4-5-6-7-8 9-8-B-A-D-C-F-E-1-0-3-2-5-4-7-6 1 0 1 0 A-B-C-D-E-F-0-1-2-3-4-5-6-7-8-9 A-B-8-9-E-F-C-D-2-3-0-1-6-7-4-5 1 0 1 1 B-C-D-E-F-0-1-2-3-4-5-6-7-8-9-A B-A-9-8-F-E-D-C-3-2-1-0-7-6-5-4 1 1 0 0 C-D-E-F-0-1-2-3-4-5-6-7-8-9-A-B C-D-E-F-8-9-A-B-4-5-6-7-0-1-2-3 1 1 0 1 D-E-F-0-1-2-3-4-5-6-7-8-9-A-B-C D-C-F-E-9-8-B-A-5-4-7-6-1-0-3-2 1 1 1 0 E-F-0-1-2-3-4-5-6-7-8-9-A-B-C-D E-F-C-D-A-B-8-9-6-7-4-5-2-3-0-1 1 1 1 1 F-0-1-2-3-4-5-6-7-8-9-A-B-C-D-E F-E-D-C-B-A-9-8-7-6-5-4-3-2-1-0 CAS Latency The CAS latency (CL) is the delay, in clock cycles, between the registration of a READ command and the availability of the first output data. The latency can be set to 2 or 3 clocks, as shown in Figure 114 (page 177). For CL = 3, if the READ command is registered at clock edge n, then the data will be nominally available at (n + 2 clocks + tAC). For CL = 2, if the READ command is registered at clock edge n, then the data will be nominally available at (n + 1 clock + tAC). PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 176 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Standard Mode Register Figure 114: CAS Latency T0 T1 READ NOP T1n T2 T2n T3 T3n CK# CK Command NOP NOP tAC CL - 1 CL = 2 DQS DQ DOUT n DOUT n+1 DOUT n+2 DOUT n+3 T2n T3 T3n T0 T1 T2 READ NOP NOP CK# CK Command NOP tAC CL - 1 CL = 3 DQS DOUT n DQ Transitioning Data DOUT n+1 Don’t Care Operating Mode The normal operating mode is selected by issuing a LOAD MODE REGISTER command with bits A[n:7] each set to zero, and bits A[6:0] set to the desired values. All other combinations of values for A[n:7] are reserved for future use. Reserved states should not be used because unknown operation or incompatibility with future versions may result. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 177 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Extended Mode Register Extended Mode Register The EMR controls additional functions beyond those set by the mode registers. These additional functions include drive strength, TCSR, and PASR. The EMR is programmed via the LOAD MODE REGISTER command with BA0 = 0 and BA1 = 1. Information in the EMR will be retained until it is programmed again, the device goes into deep power-down mode, or the device loses power. Figure 115: Extended Mode Register BA1 BA0 An n+ 2 n+ 1 n 1 0 En + 2 En + 1 0 0 0 1 1 0 1 1 En 0 – Mode Register Definition Standard mode register Status register Extended mode register Reserved ... 0 – E10 E9 0 0 – – Notes: E8 0 – E7–E0 Valid – ... A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 9 ... 10 Operation E7 0 0 0 0 1 1 1 1 8 7 E6 0 0 1 1 0 0 1 1 E5 0 1 0 1 0 1 0 1 6 DS 5 4 3 TCSR1 2 1 PASR A0 0 Address bus Extended mode register (Ex) Drive Strength Full strength 1/2 strength 1/4 strength 3/4 strength 3/4 strength Reserved Reserved Reserved Normal AR operation All other states reserved E2 0 0 0 0 1 1 1 1 E1 0 0 1 1 0 0 1 1 E0 0 1 0 Partial-Array Self Refresh Coverage Full array 1/2 array 1 0 1 0 1 Reserved Reserved 1/8 array 1/4 array 1/16 array Reserved 1. On-die temperature sensor is used in place of TCSR. Setting these bits will have no effect. 2. The integer n is equal to the most significant address bit. Temperature-Compensated Self Refresh This device includes a temperature sensor that is implemented for automatic control of the self refresh oscillator. Programming the temperature-compensated self refresh (TCSR) bits will have no effect on the device. The self refresh oscillator will continue to refresh at the optimal factory-programmed rate for the device temperature. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 178 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Extended Mode Register Partial-Array Self Refresh For further power savings during self refresh, the partial-array self refresh (PASR) feature enables the controller to select the amount of memory to be refreshed during self refresh. The refresh options include: • • • • • Full array: banks 0, 1, 2, and 3 One-half array: banks 0 and 1 One-quarter array: bank 0 One-eighth array: bank 0 with row address most significant bit (MSB) = 0 One-sixteenth array: bank 0 with row address MSB = 0 and row address MSB - 1 = 0 READ and WRITE commands can still be issued to the full array during standard operation, but only the selected regions of the array will be refreshed during self refresh. Data in regions that are not selected will be lost. Output Drive Strength Because the device is designed for use in smaller systems that are typically point-topoint connections, an option to control the drive strength of the output buffers is provided. Drive strength should be selected based on the expected loading of the memory bus. The output driver settings are 25ΩΩ, and 55Ω internal impedance for full, threequarter, and one-half drive strengths, respectively. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 179 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Status Read Register Status Read Register The status read register (SRR) is used to read the manufacturer ID, revision ID, refresh multiplier, width type, and density of the device, as shown in Figure 117 (page 181). The SRR is read via the LOAD MODE REGISTER command with BA0 = 1 and BA1 = 0. The sequence to perform an SRR command is as follows: 1. The device must be properly initialized and in the idle or all banks precharged state. 2. Issue a LOAD MODE REGISTER command with BA[1:0] = 01 and all address pins set to 0. 3. Wait tSRR; only NOP or DESELECT commands are supported during the tSRR time. 4. Issue a READ command. 5. Subsequent commands to the device must be issued tSRC after the SRR READ command is issued; only NOP or DESELECT commands are supported during tSRC. SRR output is read with a burst length of 2. SRR data is driven to the outputs on the first bit of the burst, with the output being “Don’t Care” on the second bit of the burst. Figure 116: Status Read Register Timing T0 T1 T2 T3 T4 T5 T6 T8 CK# CK tSRR Command PRE1 LMR NOP tSRC NOP2 READ NOP NOP NOP Valid tRP Address 0 BA0 = 1 BA1 = 0 BA0, BA1 &/  DQS Note 5 SRR out4 DQ Don’t Care Notes: Transitioning Data 1. All banks must be idle prior to status register read. 2. NOP or DESELECT commands are required between the LMR and READ commands (tSRR), and between the READ and the next VALID command (tSRC). 3. CAS latency is predetermined by the programming of the mode register. CL = 3 is shown as an example only. 4. Burst length is fixed to 2 for SRR regardless of the value programmed by the mode register. 5. The second bit of the data-out burst is a “Don’t Care.” PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 180 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Status Read Register Figure 117: Status Register Definition DQ31...DQ16 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 S31..S16 S15 S14 S13 S12 S11 S10 S9 S8 31..16 15 14 13 12 11 10 9 8 Type Width Refresh Rate Density Reserved1 S15 S14 S13 0 0 0 0 1 0 1 0 0 S12 0 1 0 1 1 1 1 1 0 0 1 0 1 0 1 1 1 128Mb 256Mb 512Mb 1Gb 2Gb Reserved Reserved Reserved LPDDR LPDDR2 S10 0 0 0 S9 0 0 1 S8 0 1 0 0 1 1 1 1 0 0 1 1 0 1 0 1 1 1 S7 S6 S5 S4 S3 S2 S1 S0 0 7 6 5 4 3 2 1 Revision ID Manufacturer ID Density Device Type S11 0 1 Device Width 16 bits 32 bits Refresh Multiplier2 Reserved Reserved S7 Reserved 2X 1X Reserved 0.25X Reserved Notes: DQ0 0 S6 0 S5 0 S4 0 ... ... ... ... X X X X I/O bus (CLK L->H edge) Status register S3 0 0 0 S2 0 0 0 S1 0 0 1 S0 0 1 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 0 1 1 1 1 1 0 0 1 1 0 0 0 0 1 1 0 1 0 1 1 1 0 0 Reserved 1 1 1 1 1 1 0 1 1 1 0 1 Reserved Reserved Micron Manufacturer ID Reserved Samsung Infineon Elpida Reserved Reserved Reserved Reserved Winbond ESMT NVM Reserved Revision ID The manufacturer’s revision number starts at ‘0000’ and increments by ‘0001’ each time a change in the specification (AC timings or feature set), IBIS (pullup or pull-down characteristics), or process occurs. 1. Reserved bits should be set to 0 for future compatibility. 2. Refresh multiplier is based on the memory device on-board temperature sensor. Required average periodic refresh interval = tREFI × multiplier. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 181 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Bank/Row Activation Bank/Row Activation Before any READ or WRITE commands can be issued to a bank within the device, a row in that bank must be opened. This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated (see the ACTIVE Command figure). After a row is opened with the ACTIVE command, a READ or WRITE command can be issued to that row, subject to the tRCD specification. A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous active row has been precharged. The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC. A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row access overhead. The minimum time interval between successive ACTIVE commands to different banks is defined by tRRD. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 182 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP READ Operation READ Operation READ burst operations are initiated with a READ command, as shown in Figure 106 (page 161). The starting column and bank addresses are provided with the READ command, and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the READ commands used in the following illustrations, auto precharge is disabled. During READ bursts, the valid data-out element from the starting column address will be available following the CL after the READ command. Each subsequent data-out element will be valid nominally at the next positive or negative clock edge. Figure 118 (page 184) shows general timing for each possible CL setting. DQS is driven by the device along with output data. The initial LOW state on DQS is known as the read preamble; the LOW state coincident with the last data-out element is known as the read postamble. The READ burst is considered complete when the read postamble is satisfied. Upon completion of a burst, assuming no other commands have been initiated, the DQ will go to High-Z. A detailed explanation of tDQSQ (valid data-out skew), tQH (data-out window hold), and the valid data window is depicted in Figure 125 (page 191) and Figure 126 (page 192). A detailed explanation of tDQSCK (DQS transition skew to CK) and tAC (data-out transition skew to CK) is depicted in Figure 127 (page 193). Data from any READ burst can be truncated by a READ or WRITE command to the same or alternate bank, by a BURST TERMINATE command, or by a PRECHARGE command to the same bank, provided that the auto precharge mode was not activated. Data from any READ burst can be concatenated with or truncated with data from a subsequent READ command. In either case, a continuous flow of data can be maintained. The first data element from the new burst either follows the last element of a completed burst or the last desired data element of a longer burst that is being truncated. The new READ command should be issued x cycles after the first READ command, where x equals the number of desired data element pairs (pairs are required by the 2n-prefetch architecture). This is shown in Figure 119 (page 185). A READ command can be initiated on any clock cycle following a previous READ command. Nonconsecutive read data is shown in Figure 120 (page 186). Full-speed random read accesses within a page (or pages) can be performed as shown in Figure 121 (page 187). Data from any READ burst can be truncated with a BURST TERMINATE command, as shown in Figure 122 (page 188). The BURST TERMINATE latency is equal to the READ (CAS) latency; for example, the BURST TERMINATE command should be issued x cycles after the READ command, where x equals the number of desired data element pairs (pairs are required by the 2n-prefetch architecture). Data from any READ burst must be completed or truncated before a subsequent WRITE command can be issued. If truncation is necessary, the BURST TERMINATE command must be used, as shown in Figure 123 (page 189). A READ burst can be followed by, or truncated with, a PRECHARGE command to the same bank, provided that auto precharge was not activated. The PRECHARGE command should be issued x cycles after the READ command, where x equals the number of desired data element pairs. This is shown in Figure 124 (page 190). Following the PRECHARGE command, a subsequent PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 183 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP READ Operation command to the same bank cannot be issued until tRP is met. Part of the row precharge time is hidden during the access of the last data elements. Figure 118: READ Burst CK# T0 T1 READ NOP T1n T2 T2n T3 T3n T4 T5 NOP NOP T4 T5 NOP NOP CK Command Address NOP NOP Bank a, Col n CL = 2 DQS DQ CK# DOUT n1 T0 T1 T2 READ NOP NOP DOUT n + 1 DOUT n + 2 T2n T3 DOUT n + 3 T3n CK Command Address NOP Bank a, Col n CL = 3 DQS DQ DOUT n DOUT n + 1 DOUT n + 2 DOUT n + 3 Don’t Care Notes: Transitioning Data 1. DOUT n = data-out from column n. 2. BL = 4. 3. Shown with nominal tAC, tDQSCK, and tDQSQ. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 184 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP READ Operation Figure 119: Consecutive READ Bursts T0 T1 Command READ NOP Address Bank, Col n T1n T2 T2n T3 T3n T4 T4n T5 T5n CK# CK READ NOP NOP NOP Bank, Col b CL = 2 DQS DQ DOUT n1 DOUT n+1 T2n T0 T1 T2 Command READ NOP READ Address Bank, Col n DOUT n+2 DOUT n+3 DOUT b T3 T3n T4 DOUT b+1 T4n DOUT b+2 T5 DOUT b+3 T5n CK# CK NOP NOP NOP Bank, Col b CL = 3 DQS DOUT n DQ DOUT n+1 DOUT n+2 Don’t Care Notes: DOUT n+3 DOUT b DOUT b+1 Transitioning Data 1. DOUTn (or b) = data-out from column n (or column b). 2. BL = 4, 8, or 16 (if 4, the bursts are concatenated; if 8 or 16, the second burst interrupts the first). 3. Shown with nominal tAC, tDQSCK, and tDQSQ. 4. Example applies only when READ commands are issued to same device. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 185 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP READ Operation Figure 120: Nonconsecutive READ Bursts T0 T1 Command READ NOP Address Bank, Col n T1n T2 T2n T3 T3n T4 T4n T5 T5n T6 CK# CK NOP READ NOP NOP NOP Bank, Col b CL = 2 CL = 2 DQS DOUT n1 DQ T0 T1 Command READ NOP Address Bank, Col n T1n T2 DOUT n+1 T2n DOUT n+2 DOUT n+3 T3 T3n DOUT b T4 T4n T5 DOUT b+1 T5n DOUT b+2 T6 CK# CK NOP READ NOP NOP NOP Bank, Col b CL = 3 CL = 3 DQS DOUT n DQ Notes: 1. 2. 3. 4. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 DOUT n+1 DOUT n+3 DOUT b Don’t Care Transitioning Data DOUT n+2 DOUTn (or b) = data-out from column n (or column b). BL = 4, 8, or 16 (if burst is 8 or 16, the second burst interrupts the first). Shown with nominal tAC, tDQSCK, and tDQSQ. Example applies when READ commands are issued to different devices or nonconsecutive READs. 186 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP READ Operation Figure 121: Random Read Accesses T0 T1 T1n T2 T2n T3 Command READ READ READ READ Address Bank, Col n Bank, Col x Bank, Col b Bank, Col g T3n T4 T4n T5 T5n CK# CK NOP NOP CL = 2 DQS DQ T0 T1 T1n DOUT n1 DOUT n+1 T2 T2n DOUT x DOUT x+1 DOUT b T3 T3n T4 DOUT b+1 T4n DOUT g T5 DOUT g+1 T5n CK# CK Command READ READ READ READ Address Bank, Col n Bank, Col x Bank, Col b Bank, Col g NOP NOP CL = 3 DQS DOUT n DQ DOUT n+1 DOUT x Don’t Care Notes: 1. 2. 3. 4. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 DOUT x+1 DOUT b DOUT b+1 Transitioning Data DOUTn (or x, b, g) = data-out from column n (or column x, column b, column g). BL = 2, 4, 8, or 16 (if 4, 8, or 16, the following burst interrupts the previous). READs are to an active row in any bank. Shown with nominal tAC, tDQSCK, and tDQSQ. 187 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP READ Operation Figure 122: Terminating a READ Burst T0 T1 Command READ1 BST2 Address Bank a, Col n T1n T2 T2n T3 T4 T5 NOP NOP NOP T4 T5 NOP NOP CK# CK NOP CL = 2 DQS DOUT n DQ3 T0 DOUT n+1 T1 T2 T2n BST2 NOP T3 T3n CK# CK Command READ1 Address Bank a, Col n NOP CL = 3 DQS DOUT n DQ3 DOUT n+1 Don’t Care Notes: 1. 2. 3. 4. 5. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 Transitioning Data BL = 4, 8, or 16. BST = BURST TERMINATE command; page remains open. DOUTn = data-out from column n. Shown with nominal tAC, tDQSCK, and tDQSQ. CKE = HIGH. 188 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP READ Operation Figure 123: READ-to-WRITE T0 T1 T1n T2 T2n T3 T3n T4 T4n T5 T5n CK# CK Command Address READ1 BST2 WRITE1 NOP Bank, Col n NOP NOP Bank, Col b tDQSS CL = 2 (NOM) DQS DOUT n DOUT n+1 T1 T2 T2n BST2 NOP DQ3,4 DIN b DIN b+1 DIN b+2 DIN b+3 T4 T4n T5 T5n DM T0 T3 T3n CK# CK Command Address READ1 WRITE1 NOP Bank, Col n NOP Bank, Col b tDQSS CL = 3 (NOM) DQS DOUT n DQ3,4 DOUT n+1 DIN b DIN b+1 DM Don’t Care Notes: Transitioning Data 1. BL = 4 in the cases shown (applies for bursts of 8 and 16 as well; if BL = 2, the BST command shown can be NOP). 2. BST = BURST TERMINATE command; page remains open. 3. DOUTn = data-out from column n. 4. DINb = data-in from column b. 5. Shown with nominal tAC, tDQSCK, and tDQSQ. 6. CKE = HIGH. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 189 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP READ Operation Figure 124: READ-to-PRECHARGE T0 T1 T1n T2 T2n T3 T3n T4 T5 NOP ACT3 CK# CK Command READ1 Address Banka, Col n PRE2 NOP NOP Bank a, (a or all) Bank a, Row tRP CL = 2 DQS DQ4 T0 T1 T1n DOUT n DOUT n+1 DOUT n+2 T2 T2n T3 DOUT n+3 T3n T4 T5 NOP ACT3 CK# CK Command READ1 Address Banka, Col n PRE2 NOP NOP Bank a, (a or all) Bank a, Row tRP CL = 3 DQS DOUT n DQ4 DOUT n+1 DOUT n+2 Don’t Care Notes: 1. 2. 3. 4. 5. 6. 7. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 DOUT n+3 Transitioning Data BL = 4, or an interrupted burst of 8 or 16. PRE = PRECHARGE command. ACT = ACTIVE command. DOUTn = data-out from column n. Shown with nominal tAC, tDQSCK, and tDQSQ. READ-to-PRECHARGE equals 2 clocks, which enables 2 data pairs of data-out. A READ command with auto precharge enabled, provided tRAS (MIN) is met, would cause a precharge to be performed at x number of clock cycles after the READ command, where x = BL/2. 190 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP READ Operation Figure 125: Data Output Timing – tDQSQ, tQH, and Data Valid Window (x16) CK# CK T1 T2 tHP1 T2n tHP1 T3 tHP1 tDQSQ2 tHP1 T3n tHP1 tDQSQ2 T4 tHP1 tDQSQ2 tDQSQ2 LDQS3 tQH5 tQH5 tQH5 Lower Byte DQ (Last data valid)4 DQ4 DQ4 DQ4 DQ4 DQ4 DQ4 DQ (First data no longer valid)4 tQH5 DQ (Last data valid)4 T2 T2n T3 T3n DQ (First data no longer valid)4 T2 T2n T3 T3n DQ[7:0] and LDQS, collectively6 T2 T2n T3 T3n Data valid window Data valid window Data valid window Data valid window tDQSQ2 tDQSQ2 tDQSQ2 tDQSQ2 UDQS3 tQH5 tQH5 tQH5 Upper Byte DQ (Last data valid)7 DQ7 DQ7 DQ7 DQ7 DQ7 DQ7 DQ (First data no longer valid)7 tQH5 DQ (Last data valid)7 T2 T2n DQ (First data no longer valid)7 T2 T2n collectively6 T2 T2n T3 T3n Data valid window Data valid window Data valid window Data valid window DQ[15:8] and UDQS, Notes: T3 T3 T3n T3n 1. tHP is the lesser of tCL or tCH clock transition collectively when a bank is active. 2. tDQSQ is derived at each DQS clock edge and is not cumulative over time and begins with DQS transition and ends with the last valid DQ transition. 3. DQ transitioning after DQS transitions define the tDQSQ window. LDQS defines the lower byte and UDQS defines the upper byte. 4. DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, or DQ7. 5. tQH is derived from tHP: tQH = tHP - tQHS. 6. The data valid window is derived for each DQS transitions and is defined as tQH - tDQSQ. 7. DQ8, DQ9, DQ10, DQ11, DQ12, DQ13, DQ14, or DQ15. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 191 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP READ Operation Figure 126: Data Output Timing – tDQSQ, tQH, and Data Valid Window (x32) CK# CK T1 T2 tHP1 tHP1 T2n tHP1 T3 tHP1 T3n T4 tHP1 tHP1 tDQSQ2,3 tDQSQ2,3 tDQSQ2,3 tDQSQ2,3 tQH5 tQH5 tQH5 tQH5 DQS0/DQS1/DQS2/DQS3 T2n T3 T3n DQ (First data no longer valid) T2 T2n T3 T3n DQ and DQS, collectively6,7 T2 T2n T3 T3n Data valid window Data valid window Data valid window Data valid window Notes: Byte 3 T2 Byte 2 DQ (Last data valid) Byte 1 Byte 0 DQ (Last data valid)4 DQ4 DQ4 DQ4 DQ4 DQ4 DQ4 DQ (First data no longer valid)4 1. tHP is the lesser of tCL or tCH clock transition collectively when a bank is active. 2. DQ transitioning after DQS transitions define the tDQSQ window. 3. tDQSQ is derived at each DQS clock edge and is not cumulative over time; it begins with DQS transition and ends with the last valid DQ transition. 4. Byte 0 is DQ[7:0], byte 1 is DQ[15:8], byte 2 is DQ[23:16], byte 3 is DQ[31:24]. 5. tQH is derived from tHP: tQH = tHP - tQHS. 6. The data valid window is derived for each DQS transition and is tQH - tDQSQ. 7. DQ[7:0] and DQS0 for byte 0; DQ[15:8] and DQS1 for byte 1; DQ[23:16] and DQS2 for byte 2; DQ[31:23] and DQS3 for byte 3. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 192 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP READ Operation Figure 127: Data Output Timing – tAC and tDQSCK T0 T1 T2 NOP1 NOP1 T3 T2n T3n T4 T4n T5 T5n T6 CK# CK Command READ NOP1 NOP1 NOP1 NOP1 CL = 3 tLZ tHZ tDQSCK tDQSCK tRPRE tRPST DQS or LDQS/UDQS2 tLZ All DQ values, collectively3 T2 tAC4 T2n T3 tAC4 T3n T4 T4n T5 T5n tHZ Don’t Care Notes: 1. 2. 3. 4. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 Commands other than NOP can be valid during this cycle. DQ transitioning after DQS transitions define tDQSQ window. All DQ must transition by tDQSQ after DQS transitions, regardless of tAC. tAC is the DQ output window relative to CK and is the long-term component of DQ skew. 193 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP WRITE Operation WRITE Operation WRITE bursts are initiated with a WRITE command, as shown in Figure 107 (page 162). The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the WRITE commands used in the following illustrations, auto precharge is disabled. Basic data input timing is shown in Figure 128 (page 195) (this timing applies to all WRITE operations). Input data appearing on the data bus is written to the memory array subject to the state of data mask (DM) inputs coincident with the data. If DM is registered LOW, the corresponding data will be written; if DM is registered HIGH, the corresponding data will be ignored, and the write will not be executed to that byte/column location. DM operation is illustrated in Figure 129 (page 196). During WRITE bursts, the first valid data-in element will be registered on the first rising edge of DQS following the WRITE command, and subsequent data elements will be registered on successive edges of DQS. The LOW state of DQS between the WRITE command and the first rising edge is known as the write preamble; the LOW state of DQS following the last data-in element is known as the write postamble. The WRITE burst is complete when the write postamble and tWR or tWTR are satisfied. The time between the WRITE command and the first corresponding rising edge of DQS (tDQSS) is specified with a relatively wide range (75%–125% of one clock cycle). All WRITE diagrams show the nominal case. Where the two extreme cases (that is, tDQSS [MIN] and tDQSS [MAX]) might not be obvious, they have also been included. Figure 130 (page 197) shows the nominal case and the extremes of tDQSS for a burst of 4. Upon completion of a burst, assuming no other commands have been initiated, the DQ will remain High-Z and any additional input data will be ignored. Data for any WRITE burst can be concatenated with or truncated by a subsequent WRITE command. In either case, a continuous flow of input data can be maintained. The new WRITE command can be issued on any positive edge of clock following the previous WRITE command. The first data element from the new burst is applied after either the last element of a completed burst or the last desired data element of a longer burst that is being truncated. The new WRITE command should be issued x cycles after the first WRITE command, where x equals the number of desired data element pairs (pairs are required by the 2n-prefetch architecture). Figure 131 (page 198) shows concatenated bursts of 4. An example of nonconsecutive WRITEs is shown in Figure 132 (page 198). Full-speed random write accesses within a page or pages can be performed, as shown in Figure 133 (page 199). Data for any WRITE burst can be followed by a subsequent READ command. To follow a WRITE without truncating the WRITE burst, tWTR should be met, as shown in Figure 134 (page 200). Data for any WRITE burst can be truncated by a subsequent READ command, as shown in Figure 135 (page 201). Note that only the data-in pairs that are registered prior to the tWTR period are written to the internal array, and any subsequent data-in should be masked with DM, as shown in Figure 136 (page 202). Data for any WRITE burst can be followed by a subsequent PRECHARGE command. To follow a WRITE without truncating the WRITE burst, tWR should be met, as shown in Figure 137 (page 203). PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 194 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP WRITE Operation Data for any WRITE burst can be truncated by a subsequent PRECHARGE command, as shown in Figure 138 (page 204) and Figure 139 (page 205). Note that only the data-in pairs that are registered prior to the tWR period are written to the internal array, and any subsequent data-in should be masked with DM, as shown in Figure 138 (page 204) and Figure 139 (page 205). After the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. Figure 128: Data Input Timing T01 T1 T1n T2 T2n T3 CK# CK tDSH2 tDQSS tDSS3 tDSH2 tDSS3 tDQSL tDQSH tWPST DQS4 tWPRES tWPRE DIN b DQ DM5 tDS tDH Transitioning Data Notes: 1. 2. 3. 4. Don’t Care WRITE command issued at T0. (MIN) generally occurs during tDQSS (MIN). tDSS (MIN) generally occurs during tDQSS (MAX). For x16, LDQS controls the lower byte; UDQS controls the upper byte. For x32, DQS0 controls DQ[7:0], DQS1 controls DQ[15:8], DQS2 controls DQ[23:16], and DQS3 controls DQ[31:24]. 5. For x16, LDM controls the lower byte; UDM controls the upper byte. For x32, DM0 controls DQ[7:0], DM1 controls DQ[15:8], DM2 controls DQ[23:16], and DM3 controls DQ[31:24]. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 tDSH 195 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP WRITE Operation Figure 129: Write – DM Operation T1 T0 CK# T2 T3 T4 WRITE2 NOP1 T4n T5 T5n T6 T7 NOP1 NOP11 T8 CK tIS tIH tIS tIH tCK tCH tCL CKE Command NOP1 tIS Address NOP1 ACTIVE Row Col n Row tIS BA0, BA1 PRE3 tIH tIS A10 NOP1 tIH All banks Note 4 One bank tIH Bank x Bank x5 Bank x tRCD tDQSS tWR (NOM) tRP tRAS DQS tWPRE tWPRES DIN n DQ6 tDQSL tDQSH tWPST DIN n+2 DM tDS tDH Don’t Care Notes: Transitioning Data 1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. BL = 4 in the case shown. 3. PRE = PRECHARGE. 4. Disable auto precharge. 5. Bank x at T8 is “Don’t Care” if A10 is HIGH at T8. 6. DINn = data-in from column n. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 196 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP WRITE Operation Figure 130: WRITE Burst T0 T1 T2 WRITE1,2 NOP NOP T2n T3 CK# CK Command Address t DQSS (NOM) NOP Bank a, Col b tDQSS DQS DIN b DQ3 DIN b+2 DIN b+1 DIN b+3 DM t DQSS (MIN) tDQSS DQS DQ3 DIN b DIN b+1 DIN b+2 DIN b+3 DIN b DIN b+1 DIN b+2 DM t DQSS (MAX) tDQSS DQS DQ3 DIN b+3 DM Don’t Care Notes: Transitioning Data 1. An uninterrupted burst of 4 is shown. 2. A10 is LOW with the WRITE command (auto precharge is disabled). 3. DINb = data-in for column b. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 197 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP WRITE Operation Figure 131: Consecutive WRITE-to-WRITE T0 T1 WRITE1, 2 NOP T1n T2 T2n T3 T3n T4 T4n T5 CK# CK Command Address WRITE1, 2 Bank, Col b tDQSS NOP NOP NOP Bank, Col n (NOM) DQS DIN b DQ3 DIN b+1 DIN b+2 DIN b+3 DIN n DIN n+1 DIN n+2 DIN n+3 DM Don’t Care Notes: Transitioning Data 1. Each WRITE command can be to any bank. 2. An uninterrupted burst of 4 is shown. 3. DINb (n) = data-in for column b (n). Figure 132: Nonconsecutive WRITE-to-WRITE T0 T1 WRITE1, 2 NOP T1n T2 T2n T3 T4 T4n T5 T5n CK# CK Command Address WRITE1,2 NOP Bank, Col b tDQSS NOP NOP Bank, Col n (NOM) DQS DIN b DQ3 DIN b+1 DIN b+2 DIN b+3 DIN n DIN n+1 DIN n+2 DIN n+3 DM Don’t Care Notes: Transitioning Data 1. Each WRITE command can be to any bank. 2. An uninterrupted burst of 4 is shown. 3. DINb (n) = data-in for column b (n). PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 198 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP WRITE Operation Figure 133: Random WRITE Cycles T0 T1 T1n T2 T2n T3 T3n T4 WRITE1,2 WRITE1,2 WRITE1,2 WRITE1,2 WRITE1,2 Bank, Col b Bank, Col x Bank, Col n Bank, Col a Bank, Col g T4n T5 T5n CK# CK Command Address tDQSS NOP (NOM) DQS DIN b DQ3,4 DIN b’ DIN x DIN x’ DIN n DIN n’ DIN a DIN a’ DIN g DIN g’ DM Don’t Care Notes: 1. 2. 3. 4. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 Transitioning Data Each WRITE command can be to any bank. Programmed BL = 2, 4, 8, or 16 in cases shown. DINb (or x, n, a, g) = data-in for column b (or x, n, a, g). b' (or x, n, a, g) = the next data-in following DINb (x, n, a, g) according to the programmed burst order. 199 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP WRITE Operation Figure 134: WRITE-to-READ – Uninterrupting T0 T1 WRITE2,3 NOP T1n T2 T2n T3 T4 T5 READ NOP T5n T6 T6n CK# CK Command1 NOP NOP NOP tWTR4 Address t DQSSnom Bank a, Col b Bank a, Col n tDQSS CL = 2 DQS DIN b DQ5 DIN b+2 DIN b+1 DIN b+3 DOUT n DOUT n+1 DOUT n DOUT n+1 DOUT n DOUT n+1 DM t DQSSmin tDQSS CL = 2 DQS DIN b DQ5 DIN b+1 DIN b+2 DIN b+3 DM t DQSSmax tDQSS CL = 2 DQS DIN b DQ5 DIN b+1 DIN b+2 DIN b+3 DM Don’t Care Notes: Transitioning Data 1. The READ and WRITE commands are to the same device. However, the READ and WRITE commands may be to different devices, in which case tWTR is not required and the READ command could be applied earlier. 2. A10 is LOW with the WRITE command (auto precharge is disabled). 3. An uninterrupted burst of 4 is shown. 4. tWTR is referenced from the first positive CK edge after the last data-in pair. 5. DINb = data-in for column b; DOUTn = data-out for column n. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 200 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP WRITE Operation Figure 135: WRITE-to-READ – Interrupting T0 T1 WRITE1,2 NOP T1n T2 T2n T3 T4 T5 NOP NOP T5n T6 T6n CK# CK Command NOP READ NOP tWTR3 Address t DQSS (NOM) Bank a, Col b Bank a, Col n tDQSS CL = 3 DQS4 DIN b DQ5 DIN b+1 DOUT n DOUT n+1 DM t DQSS (MIN) tDQSS CL = 3 DQS4 DIN b DQ5 DIN b+1 DOUT n DOUT n+1 DM t DQSS (MAX) tDQSS CL = 3 DQS4 DIN b DQ5 DIN b+1 DOUT n DOUT n+1 DM Don’t Care Notes: 1. 2. 3. 4. 5. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 Transitioning Data An interrupted burst of 4 is shown; 2 data elements are written. A10 is LOW with the WRITE command (auto precharge is disabled). tWTR is referenced from the first positive CK edge after the last data-in pair. DQS is required at T2 and T2n (nominal case) to register DM. DINb = data-in for column b; DOUTn = data-out for column n. 201 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP WRITE Operation Figure 136: WRITE-to-READ – Odd Number of Data, Interrupting T0 T1 WRITE2 NOP T1n T2 T2n T3 T4 T5 NOP NOP T5n T6 T6n CK# CK Command1 NOP READ NOP tWTR3 Address t DQSS (NOM) Bank a, Col b Bank a, Col b tDQSS CL = 3 DQS4 DIN b DQ5 DOUT n DOUT n+1 DM t DQSS (MIN) tDQSS CL = 3 DQS4 DIN b DQ5 DOUT n DOUT n+1 DM t DQSS (MAX) tDQSS CL = 3 DQS4 DOUT n DIN b DQ5 DOUT n+1 DM Don’t Care Notes: 1. 2. 3. 4. 5. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 Transitioning Data An interrupted burst of 4 is shown; 1 data element is written, 3 are masked. A10 is LOW with the WRITE command (auto precharge is disabled). tWTR is referenced from the first positive CK edge after the last data-in pair. DQS is required at T2 and T2n (nominal case) to register DM. DINb = data-in for column b; DOUTn = data-out for column n. 202 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP WRITE Operation Figure 137: WRITE-to-PRECHARGE – Uninterrupting T0 T1 T1n WRITE2,4 NOP T2 T2n T3 T4 T5 T6 NOP NOP PRE3,4 NOP CK# CK Command1 NOP tWR5 Address t DQSS (NOM)  Bank a, Col b Bank (a or all) tDQSS DQS DIN b DQ6 DIN b+1 DIN b+2 DIN b+3 DM t DQSS (MIN) tDQSS DQS DIN b DQ6 DIN b+1 DIN b+2 DIN b+3 DIN b DIN b+1 DIN b+2 DM t DQSS tDQSS (MAX) DQS DQ6 DIN b+3 DM Don’t Care Notes: Transitioning Data 1. 2. 3. 4. An uninterrupted burst 4 of is shown. A10 is LOW with the WRITE command (auto precharge is disabled). PRE = PRECHARGE. The PRECHARGE and WRITE commands are to the same device. However, the PRECHARGE and WRITE commands can be to different devices; in this case, tWR is not required and the PRECHARGE command can be applied earlier. 5. tWR is referenced from the first positive CK edge after the last data-in pair. 6. DINb = data-in for column b. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 203 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP WRITE Operation Figure 138: WRITE-to-PRECHARGE – Interrupting CK# T0 T1 T1n WRITE2 NOP T2 T2n T3 T3n T4 T4n T5 T6 NOP NOP CK Command1 NOP NOP PRE3 tWR4 Bank a, Col b Address t DQSS (NOM) Bank (a or all) tDQSS DQS5 DIN b DQ6 DIN b+1 DM t DQSS (MIN) tDQSS DQS5 DIN b DQ6 DIN b+1 DM t DQSS (MAX) tDQSS DQS5 DIN b DQ6 DIN b+1 DM Don’t Care Notes: 1. 2. 3. 4. 5. 6. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 Transitioning Data An interrupted burst of 8 is shown; two data elements are written. A10 is LOW with the WRITE command (auto precharge is disabled). PRE = PRECHARGE. tWR is referenced from the first positive CK edge after the last data-in pair. DQS is required at T4 and T4n to register DM. DINb = data-in for column b. 204 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP WRITE Operation Figure 139: WRITE-to-PRECHARGE – Odd Number of Data, Interrupting CK# T0 T1 WRITE2 NOP T1n T2 T2n T3 T3n T4 T4n T5 T6 PRE3 NOP CK Command1 NOP NOP NOP tWR4 Address t DQSS (NOM) Bank a, Col b Bank (a or all) tDQSS DQS5, 6 DIN b DQ7 DM6 t DQSS (MIN) tDQSS DQS5, 6 DIN b DQ7 DM6 t DQSS (MAX) tDQSS DQS5, 6 DIN b DQ7 DM6 Don’t Care Notes: 1. 2. 3. 4. 5. 6. 7. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 Transitioning Data An interrupted burst of 8 is shown; one data element is written. A10 is LOW with the WRITE command (auto precharge is disabled). PRE = PRECHARGE. tWR is referenced from the first positive CK edge after the last data-in pair. DQS is required at T4 and T4n to register DM. If a burst of 4 is used, DQS and DM are not required at T3, T3n, T4, and T4n. DINb = data-in for column b. 205 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP PRECHARGE Operation PRECHARGE Operation The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access some specified time (tRP) after the PRECHARGE command is issued. Input A10 determines whether one or all banks will be precharged, and in the case where only one bank is precharged (A10 = LOW), inputs BA0 and BA1 select the bank. When all banks are precharged (A10 = HIGH), inputs BA0 and BA1 are treated as “Don’t Care.” After a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. A PRECHARGE command will be treated as a NOP if there is no open row in that bank (idle state), or if the previously open row is already in the process of precharging. Auto Precharge Auto precharge is a feature that performs the same individual bank PRECHARGE function described previously, without requiring an explicit command. This is accomplished by using A10 to enable auto precharge in conjunction with a specific READ or WRITE command. A precharge of the bank/row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or WRITE burst. Auto precharge is nonpersistent; it is either enabled or disabled for each individual READ or WRITE command. Auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. This earliest valid stage is determined as if an explicit PRECHARGE command was issued at the earliest possible time without violating tRAS (MIN), as described for each burst type in Table 53 (page 167). The READ with auto precharge enabled state or the WRITE with auto precharge enabled state can each be broken into two parts: the access period and the precharge period. The access period starts with registration of the command and ends where tRP (the precharge period) begins. For READ with auto precharge, the precharge period is defined as if the same burst was executed with auto precharge disabled, followed by the earliest possible PRECHARGE command that still accesses all the data in the burst. For WRITE with auto precharge, the precharge period begins when tWR ends, with tWR measured as if auto precharge was disabled. In addition, during a WRITE with auto precharge, at least one clock is required during tWR time. During the precharge period, the user must not issue another command to the same bank until tRP is satisfied. This device supports tRAS lock-out. In the case of a single READ with auto precharge or single WRITE with auto precharge issued at tRCD (MIN), the internal precharge will be delayed until tRAS (MIN) has been satisfied. Bank READ operations with and without auto precharge are shown in Figure 140 (page 208) and Figure 141 (page 210). Bank WRITE operations with and without auto precharge are shown in Figure 142 (page 211) and Figure 143 (page 212). PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 206 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Auto Precharge Concurrent Auto Precharge This device supports concurrent auto precharge such that when a READ with auto precharge is enabled or a WRITE with auto precharge is enabled, any command to another bank is supported, as long as that command does not interrupt the read or write data transfer already in process. This feature enables the precharge to complete in the bank in which the READ or WRITE with auto precharge was executed, without requiring an explicit PRECHARGE command, thus freeing the command bus for operations in other banks. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 207 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Auto Precharge Figure 140: Bank Read – With Auto Precharge CK# T1 T0 T2 T3 T4 T5 T5n T6 T6n T7 T8 CK tIS tCK tIH tCH tCL CKE tIS Command tIH NOP1 ACTIVE tIS NOP1 READ2 NOP1 NOP1 NOP1 NOP1 ACTIVE tIH Address Row A10 Row Col n Row Note 3 Row tIS tIS BA0, BA1 tIH tIH Bank x Bank x Bank x tRCD tRP tRAS tRC DM CL = 2 Case 1: tAC (MIN) and tDQSCK (MIN) tDQSCK tRPRE tRPST (MIN) DQS4 tLZ tAC (MIN) (MIN) DOUT n DQ4,5 tLZ Case 2: tAC (MAX) and tDQSCK (MAX) DOUT n+1 DOUT x DOUT x+1 (MIN) tRPRE tDQSCK tRPST (MAX) DQS4 DOUT n DQ4,5 tAC (MAX) DOUT n+1 DOUT x tHZ DOUT x+1 (MAX) Don’t Care Notes: Transitioning Data 1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. BL = 4 in the case shown. 3. Enable auto precharge. 4. Refer to Figure 125 (page 191) and Figure 126 (page 192) for detailed DQS and DQ timing. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 208 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Auto Precharge 5. DOUT n = data-out from column n. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 209 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Auto Precharge Figure 141: Bank Read – Without Auto Precharge CK# T1 T0 T2 T3 T4 T5 T5n READ2 NOP1 PRE3 T6 T6n T7 T8 NOP1 ACTIVE CK tIS tIH tIS tIH tCK tCH tCL CKE Command NOP1 NOP1 ACTIVE tIS Row Address Col n tIS A10 NOP1 tIH Row Row tIH All banks Row Note 4 One bank tIS BA0, BA1 tIH Bank x Bank x5 Bank x Bank x tRCD tRP tRAS6 tRC DM CL = 2 Case 1: tAC (MIN) and tDQSCK (MIN) tDQSCK tRPRE tRPST (MIN) DQS7 tLZ (MIN) tAC (MIN) DOUT n DQ7,8 tLZ DOUT n+1 DOUT n+2 DOUT n+3 (MIN) Case 2: tAC (MAX) and tDQSCK (MAX) tRPRE tDQSCK tRPST (MAX) DQS7 DOUT n DQ7,8 tAC (MAX) DOUT n+1 DOUT n+2 DOUT n+3 tHZ (MAX) Don’t Care Notes: Transitioning Data 1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. BL = 4 in the case shown. 3. PRE = PRECHARGE. 4. Disable auto precharge. 5. Bank x at T5 is “Don’t Care” if A10 is HIGH at T5. 6. The PRECHARGE command can only be applied at T5 if tRAS (MIN) is met. 7. Refer to Figure 125 (page 191) and Figure 126 (page 192) for DQS and DQ timing details. 8. DOUTn = data out from column n. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 210 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Auto Precharge Figure 142: Bank Write – With Auto Precharge CK# CK T1 T0 tIS T2 tIH tCK T3 tCH T4 T4n T5 T5n T6 T7 T8 tCL CKE tIS Command tIH NOP4 NOP4 ACTIVE tIS WRITE2 NOP4 NOP4 NOP4 NOP4 NOP4 tIH Address Row A10 Row Col n Note 3 tIS BA0, BA1 tIS tIH tIH Bank x Bank x tRCD tDQSS tWR (NOM) tRP tRAS DQS tWPRE tWPRES tDQSL tDQSH tWPST DIN b DQ1 DM tDS tDH Don’t Care Notes: Transitioning Data 1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. BL = 4 in the case shown. 3. Enable auto precharge. 4. DINn = data-out from column n. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 211 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Auto Precharge Figure 143: Bank Write – Without Auto Precharge CK T1 T0 CK# tIS T2 tIH tCK T3 tCH T4 T4n T5 T5n T6 T7 T8 NOP1 NOP1 PRE3 tCL CKE tIS Command tIH NOP1 tIS Address NOP1 ACTIVE WRITE2 tIH Row Col n tIS A10 Row tIS BA0, BA1 NOP1 NOP1 tIH All banks Note 4 One bank tIH Bank x Bank x5 Bank x tWR tRCD tRP tRAS tDQSS (NOM) DQS tWPRES tWPRE tDQSL tDQSH tWPST DIN b DQ6 DM tDS tDH Notes: Don’t Care Transitioning Data 1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. BL = 4 in the case shown. 3. PRE = PRECHARGE. 4. Disable auto precharge. 5. Bank x at T8 is “Don’t Care” if A10 is HIGH at T8. 6. DOUTn = data-out from column n. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 212 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP AUTO REFRESH Operation AUTO REFRESH Operation Auto refresh mode is used during normal operation of the device and is analogous to CAS#-BEFORE-RAS# (CBR) REFRESH in FPM/EDO DRAM. The AUTO REFRESH command is nonpersistent and must be issued each time a refresh is required. The addressing is generated by the internal refresh controller. This makes the address bits a “Don’t Care” during an AUTO REFRESH command. For improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. The auto refresh period begins when the AUTO REFRESH command is registered and ends tRFC later. Figure 144: Auto Refresh Mode T0 T2 T1 T3 T4 CK# CK tIS tCK tIH CKE tCL tIH NOP 2 NOP2 PRE Ta0 Ta1 )) (( )) Valid tIS Command1 tCH (( )) (( )) NOP2 AR )) (( )) NOP2, 3 AR4 (( )) (( )) Tb0 )) (( )) Valid (( )) (( )) NOP2, 3 Tb1 Tb2 NOP2 ACTIVE (( )) (( )) (( )) (( )) Row (( )) (( )) (( )) (( )) Row (( )) (( )) (( )) (( )) Bank DQS6 (( )) (( )) (( )) (( )) DQ6 (( )) (( )) (( )) (( )) DM6 (( )) (( )) (( )) (( )) Address All banks A10 One bank BA0, BA1 Bank(s)5 tRP tRFC tRFC4 Don’t Care Notes: 1. PRE = PRECHARGE; AR = AUTO REFRESH. 2. NOP commands are shown for ease of illustration; other commands may be valid during this time. CKE must be active during clock positive transitions. 3. NOP or COMMAND INHIBIT are the only commands supported until after tRFC time; CKE must be active during clock positive transitions. 4. The second AUTO REFRESH is not required and is only shown as an example of two back-to-back AUTO REFRESH commands. 5. Bank x at T1 is “Don’t Care” if A10 is HIGH at this point; A10 must be HIGH if more than one bank is active (for example, must precharge all active banks). 6. DM, DQ, and DQS signals are all “Don’t Care”/High-Z for operations shown. Although it is not a JEDEC requirement, CKE must be active (HIGH) during the auto refresh period to provide support for future functional features. The auto refresh period begins when the AUTO REFRESH command is registered and ends tRFC later. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 213 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP SELF REFRESH Operation SELF REFRESH Operation The SELF REFRESH command can be used to retain data in the device while the rest of the system is powered down. When in self refresh mode, the device retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command, except that CKE is disabled (LOW). All command and address input signals except CKE are “Don’t Care” during self refresh. During self refresh, the device is refreshed as defined in the extended mode register. (see Partial-Array Self Refresh (page 179).) An internal temperature sensor adjusts the refresh rate to optimize device power consumption while ensuring data integrity. (See Temperature-Compensated Self Refresh (page 178).) The procedure for exiting self refresh requires a sequence of commands. First, CK must be stable prior to CKE going HIGH. When CKE is HIGH, the device must have NOP commands issued for tXSR to complete any internal refresh already in progress. During SELF REFRESH operation, refresh intervals are scheduled internally and may vary. These refresh intervals may differ from the specified tREFI time. For this reason, the SELF REFRESH command must not be used as a substitute for the AUTO REFRESH command. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 214 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Power-Down Figure 145: Self Refresh Mode T0 T1 CK# CK1 tCH tIS tIH tCL tIS tCKE CKE1,2 tIS Command Ta01 Ta1 tCK tIS AR3 (( )) (( )) (( )) (( )) NOP (( )) (( )) Address (( )) (( )) (( )) (( )) DQS (( )) (( )) (( )) (( )) DQ (( )) (( )) (( )) (( )) DM (( )) (( )) (( )) (( )) tRP4 Tb0 (( )) (( )) (( )) tIH NOP (( )) (( )) Valid tIS tIH Valid tXSR5 Enter self refresh mode Exit self refresh mode Don’t Care Notes: 1. Clock must be stable, cycling within specifications by Ta0, before exiting self refresh mode. 2. CKE must remain LOW to remain in self refresh. 3. AR = AUTO REFRESH. 4. Device must be in the all banks idle state prior to entering self refresh mode. 5. Either a NOP or DESELECT command is required for tXSR time with at least two clock pulses. Power-Down Power-down is entered when CKE is registered LOW. If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. Entering power-down deactivates all input and output buffers, including CK and CK# and excluding CKE. Exiting power-down requires the device to be at the same voltage as when it entered power-down and received a stable clock. Note that the power-down duration is limited by the refresh requirements of the device. When in power-down, CKE LOW must be maintained at the inputs of the device, while all other input signals are “Don’t Care.” The power-down state is synchronously exited when CKE is registered HIGH (in conjunction with a NOP or DESELECT command). NOP or DESELECT commands must be maintained on the command bus until tXP is satisfied. See Figure 147 (page 217) for a detailed illustration of power-down mode. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 215 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Power-Down Figure 146: Power-Down Entry (in Active or Precharge Mode) CK# CK CKE CS# RAS#, CAS#, WE# Or CS# RAS#, CAS#, WE# Address BA0, BA1 Don’t Care PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 216 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Power-Down Figure 147: Power-Down Mode (Active or Precharge) T0 T1 T2 CK# CK tCK tIS tCH tIS tIH CKE tCKE Ta2 Tb1 tCKE1 tXP1 tIH Valid2 tIS Address Ta1 (( )) tIS Command tCL Ta0 (( )) (( )) NOP tIH (( )) (( )) NOP (( )) (( )) Valid DQS (( )) (( )) DQ (( )) (( )) DM (( )) (( )) Valid Valid Must not exceed refresh device limits No read/write Enter3 access in progress power-down mode Notes: Exit power-down mode Don’t Care 1. tCKE applies if CKE goes LOW at Ta2 (entering power-down); tXP applies if CKE remains HIGH at Ta2 (exit power-down). 2. If this command is a PRECHARGE (or if the device is already in the idle state), then the power-down mode shown is precharge power-down. If this command is an ACTIVE (or if at least 1 row is already active), then the power-down mode shown is active powerdown. 3. No column accesses can be in progress when power-down is entered. Deep Power-Down Deep power-down (DPD) is an operating mode used to achieve maximum power reduction by eliminating power to the memory array. Data will not be retained after the device enters DPD mode. Before entering DPD mode the device must be in the all banks idle state with no activity on the data bus (tRP time must be met). DPD mode is entered by holding CS# and WE# LOW with RAS# and CAS# HIGH at the rising edge of the clock while CKE is LOW. CKE must be held LOW to maintain DPD mode. The clock must be stable prior to exiting DPD mode. To exit DPD mode, assert CKE HIGH with either a NOP or DESELECT command present on the command bus. After exiting DPD mode, a full DRAM initialization sequence is required. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 217 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Power-Down Figure 148: Deep Power-Down Mode T0 T1 CK# Ta1 Ta2 Ta3 )) (( )) CK tIS tCKE CKE Command1 Ta01 T2 ( ( (( )) DPD2 NOP All banks idle with no activity on the data bus T = 200μs (( )) (( )) NOP Enter deep power-down mode PRE3 NOP Exit deep power-down mode Don’t Care Notes: 1. Clock must be stable prior to CKE going HIGH. 2. DPD = deep power-down. 3. Upon exit of deep power-down mode, a full DRAM initialization sequence is required. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 218 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Clock Change Frequency Clock Change Frequency One method of controlling the power efficiency in applications is to throttle the clock that controls the device. The clock can be controlled by changing the clock frequency or stopping the clock. The device enables the clock to change frequency during operation only if all timing parameters are met and all refresh requirements are satisfied. The clock can be stopped altogether if there are no DRAM operations in progress that would be affected by this change. Any DRAM operation already in process must be completed before entering clock stop mode; this includes the following timings: tRCD, tRP, tRFC, tMRD, tWR, and tRPST. In addition, any READ or WRITE burst in progress must be complete. (See READ Operation and WRITE Operation.) CKE must be held HIGH with CK = LOW and CK# = HIGH for the full duration of the clock stop mode. One clock cycle and at least one NOP or DESELECT is required after the clock is restarted before a valid command can be issued. Figure 149: Clock Stop Mode Ta1 CK# CK CKE Ta2 Tb3 ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) (( )) (( )) Command ( ( ) ) ( ( ) ) Address ( ( ) ) ( ( ) ) DQ, DQS (( )) (( )) NOP1 (( )) (( )) (( )) ( ( ) ) 2 ( ( CMD ) ) CMD2 ( ( ) ) ( ( ) ) Valid (( )) (( )) Tb4 Valid NOP NOP (( )) (( )) (( )) (( )) (( )) (( )) All DRAM activities must be complete Exit clock stop mode Enter clock stop mode Don’t Care Notes: 1. Prior to Ta1, the device is in clock stop mode. To exit, at least one NOP is required before issuing any valid command. 2. Any valid command is supported; device is not in clock suspend mode. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 219 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP Revision History Revision History Rev. C – 12/12 • Format correction in Features Rev. B – 10/12 • Added new industrial temperature (IT) part numbers • Added industrial temperature range under Features Rev. A – 05/11 • Initial release; Preliminary status 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 www.micron.com/productsupport Customer Comment Line: 800-932-4992 Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef846d1f3b 168ball_nand_lpddr_j4p2_j4x2_j4x3_omap.pdf - Rev. C 12/12 220 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2011 Micron Technology, Inc. All rights reserved.
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